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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu
TL;DR
Logic synthesis and physical design can be mis-correlated, and front-end optimization gains may diminish after mapping. PigMAP uses approximate primitive-gate placement to obtain spatial information for wirelength-based mapping, with schemes targeting critical-path or total wirelength. EPFL benchmarks: PigMAP-Performance reduces post-routing delay by 14% with a 6% increase in power; PigMAP-Power improves post-routing delay by 3% and reduces power consumption by 9%.
Problem
Logic synthesis and physical design can be mis-correlated, and front-end optimization gains may diminish after mapping.
Source: §1 · p. 1Method
PigMAP uses approximate primitive-gate placement to obtain spatial information for wirelength-based mapping, with schemes targeting critical-path or total wirelength.
Source: §1 · p. 2Results
EPFL benchmarks: PigMAP-Performance reduces post-routing delay by 14% with a 6% increase in power; PigMAP-Power improves post-routing delay by 3% and reduces power consumption by 9%.
Source: §1 · p. 2Takeaways & Limitations
An effective flow should incorporate an efficient mapping algorithm that uses placement-based physical information.
Source: §1 · p. 1
Abstract
from arXiv · showhide
A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption.
1 INTRODUCTION
Physically aware synthesis faces a gap between front-end logic optimization and back-end physical outcomes, alongside limitations in how mapping uses physical feedback. PigMAP combines primitive-gate placement with wirelength-driven mapping to generate physically aware netlists.
1 INTRODUCTION
- Front-end logic-optimization gains can diminish after mapping, and omitting those optimizations shifts final delay only from 73% to 77%, illustrating stage miscorrelation.The introduction also identifies limited topology in gate-level resynthesis and inefficiency in broader mapping approaches as limitations of prior methods.Source: §1 · p. 1
- PigMAP uses approximate primitive-gate placement to obtain technology-independent spatial information for wirelength-based mapping and physically friendly netlists.Its two schemes constrain either critical-path wirelength for performance or total wirelength for power.Source: §1 · p. 2
- The framework estimates potential wirelength between AIG nodes and introduces virtual wirelength, a placement-derived metric that adds interconnect awareness to mapping.Source: §1 · p. 2
- Across the EPFL benchmark suites, PigMAP-Performance reduces post-routing delay by 14% with only a 6% increase in power consumption, while PigMAP-Power improves post-routing delay by 3% and reduces power consumption by 9%.Source: §1 · p. 2
2 BACKGROUND
The background establishes Boolean-network and AIG representations, then reviews technology mapping and physically aware synthesis that incorporates placement information into mapping.
2 BACKGROUND
- The background reviews Boolean networks, technology mapping, physically aware synthesis, and place-and-route; Table 1 lists PigMAP notation and parameters.Source: §2 · p. 2, Table 1 · p. 2
2.1 Boolean Network and AIG
- An AIG represents a Boolean network using two-input AND gates and inverter edges, with size and depth as its primary metrics.Source: §2.1 · p. 2
2.2 Technology Mapping
- Technology mapping translates a Boolean network into library primitives by enumerating feasible cuts, matching cells, and selecting a graph cover under a cost function.Source: §2.2 · p. 3
2.2.1 Delay-driven mapping.
- Delay-driven mapping retains timing-favorable gate and cut candidates, computes node delay from the maximum leaf delay plus cell delay, then backpropagates timing constraints.Source: §2.2.1 · p. 3
2.2.2 Area-driven mapping.
- Area-driven mapping optimizes area under timing constraints, using area flow to estimate the mapped area from a node toward accessible primary inputs.Area flow incorporates the node's gate area and estimated fanouts.Source: §2.2.2 · p. 3
2.3 Physically aware Synthesis
- Physically aware synthesis can use placement, load, congestion, and post-routing information; PigMAP moves this synthesis into technology mapping rather than iterating on a post-placement netlist.Source: §2.3 · p. 3
2.4 Place-and-route
- Placement minimizes total wirelength subject to density constraints, while routing uses placement output and global-routing guides for detailed signal and clock routing.Source: §2.4 · pp. 3–4
3 OUR APPROACH
PigMAP combines approximate placement of AIG nodes with placement-aware technology mapping to guide synthesis using wirelength constraints. Its performance and power strategies optimize different wirelength objectives within a staged mapping flow.
3 OUR APPROACH
- PigMAP places AIG nodes, performs delay- and area-driven mapping, refines the mapping with wirelength constraints, and then generates the final gate-level netlist.The framework also applies detailed area optimization under wirelength constraints.Source: §3 · p. 4
3.1 PigMAP-Placer: Primitive Logic Gate Placement
- A graph-convolution-based placer estimates optimized relative node positions, providing spatial information for wirelength-aware mapping.The example notes that mapping nodes 6 and 9 into one cell can reduce netlist wirelength.Source: §3.1 · pp. 4–5
3.2 PigMAP-Mapper: Placement-aware Mapping
- Mapping preparation selects library supergates for each cut and searches for pins, defined as cut roots and parents of cut leaves.The pin search uses a maximum depth; the mapper then evaluates both signal phases and tracks critical-path wirelength, total wirelength, delay, and area.Source: §3.2 · p. 5
- The performance strategy targets maximum wirelength, while the power strategy targets total circuit wirelength.The total-wirelength metric aggregates discounted paths accessed by leaves.Source: §3.2 · p. 5
- The mapper evaluates delay, area, and two wirelength metrics for candidate supergates, pruning choices that violate arrival-time or maximum-wirelength constraints.Performance mapping weighs arrival time and maximum wirelength; power mapping prioritizes total wirelength after rejecting excessive arrival times, with an additional global-area consideration.Source: §3.2 · p. 6
4 EXPERIMENTAL RESULTS
PigMAP’s two mapping schemes trade critical-path delay and power, with evaluation spanning mapping behavior, routed results, and a Bar case study.
4 EXPERIMENTAL RESULTS
- Evaluation used EPFL combinational benchmarks routed in ASAP7 with OpenROAD, comparing PigMAP with Yosys/OpenROAD and OpenPhySyn under consistent core area and zero-slack clocks.The experiments included mapping-and-routing analysis and end-to-end comparisons of final delay, area, power, and runtime.Source: §4 · p. 6, §4.1 · pp. 6–7
4.1 Experimental Results and Analysis
- Against the baseline, PigMAP-Performance reduces delay 14% (area +8%, power +6%), while PigMAP-Power reduces delay 3% (power -9%, area +3%).Table 2 reports final results from the OpenROAD flow with ASAP 7nm technology.Source: Table 2 · p. 7, §4.1.1 · p. 7, §4.1.2 · p. 7
4.1.1 PigMAP-Performance.
- PigMAP-Performance improved virtual wirelength by up to 57% for a 5% area increase, then reduced routed delay 14%; on 16 successful OpenPhySyn cases, it cut delay 9% but raised power 3%.OpenPhySyn failed to produce results on 4 of 20 benchmarks; the Figure 7 caption identifies the mapping and routing results.Source: §4.1.1 · p. 7, Figure 7 · p. 8
4.1.2 PigMAP-Power.
- PigMAP-Power trades 1% more mapped delay for 22% better virtual total wirelength, while routed total wirelength improves 3%; total runtime is 1.61× slower.The mode also increases critical-path virtual wirelength by 8%; the paper notes that virtual total wirelength can affect routed total wirelength and final power.Source: §4.1.2 · pp. 7–8, Figure 7 · p. 8
4.2 Case Study
- On Bar, PigMAP-Performance’s critical path has fewer routing detours; PigMAP-Power reduces interconnects on a same-I/O noncritical path, lowering power consumption.Figure 8 shows the final layouts, with the critical path marked in red.Source: Figure 8 · p. 8, §4.2 · p. 8
5 CONCLUSION
PigMAP uses wirelength constraints to guide mapping toward lower critical-path delay or power consumption, with distinct Performance and Power schemes.
5 CONCLUSION
- PigMAP-Performance targets critical-path delay, reducing it 14% with a slight power increase, while PigMAP-Power targets power, reducing it 9% and improving delay 3%.The conclusion presents the schemes as addressing distinct optimization goals.Source: §5 · p. 8