Source-linked AI summary
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu
TL;DR
As interconnect delays dominate gate delays, traditional logic-depth metrics are insufficient for timing closure. LevelSyn uses a level-aware GNN to map AIG structure to spatial priors, reporting 6.89% average power reduction, 27.48% timing-delay reduction, and 99.59% fewer post-place-and-route DRC violations.
Problem
As interconnect delays dominate gate delays, traditional logic-depth metrics are insufficient for timing closure.
Source: §2.1 · p. 2Method
LevelSyn combines a level-aware GNN mapping AIG structure to spatial priors with an end-to-end physical-aware synthesis flow.
Source: §3.1 · p. 2, §3.2 · p. 3Results
LevelSyn reports 6.89% average power reduction, 27.48% timing-delay reduction, and 99.59% fewer DRC violations after place-and-route.
Source: §1 · p. 2Takeaways & Limitations
Post-place-and-route validation indicates LevelSyn generates layout-friendly netlists and accelerates design convergence.
Source: §1 · p. 2Standard GNNs face GPU-memory demands and inference-latency overhead on large netlists, which can outweigh accuracy benefits.
Source: §2.2 · p. 2
Abstract
from arXiv · showhide
As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies on non-physical Wire Load Models (WLMs), while recent spectral-based placement predictors often neglect the inherent hierarchical logic depth and signal flow of netlists, which leads to low-fidelity spatial estimations. To bridge this gap, we propose LevelSyn, a novel physical-aware logic synthesis framework that integrates hierarchical representation learning with a wirelength-driven optimization engine. At its core, LevelSyn leverages a level-asynchronous Graph Neural Network (GNN) to predict high-fidelity gate coordinates by capturing the structural and directional semantics of And-Inverter Graphs (AIGs). To handle industrial-scale designs, a level-aligned subgraph partitioning strategy is introduced to eliminate memory bottlenecks while preserving local logical dependencies. These spatial insights are seamlessly integrated into a newly developed physical-informed synthesis engine within the Berkeley ABC framework. Experimental results on the EPFL benchmark suite demonstrate that LevelSyn significantly outperforms state-of-the-art (SOTA) methods, achieving an average power reduction of 6.89\% and a timing delay improvement of 27.48\%. Furthermore, post-place-and-route validation shows a 99.59\% reduction in design rule check (DRC) violations, highlighting its effectiveness in accelerating design convergence.
1 Introduction
LevelSyn bridges logic synthesis and physical implementation by predicting layout-aware spatial guidance for ABC; the introduction reports improved EPFL power and timing results and fewer post-place-and-route DRC violations.
1 Introduction
- The shift-left strategy [35] exposes future design metrics and potential violations earlier, while physical-aware synthesis uses backend information to estimate interconnect delay and congestion beyond logical-only models.The introduction notes that synthesis results may be poorly suited to modern nanometer-scale physical implementation.Source: §1 · p. 1
- Net2 [37] and use GNNs for pre-placement wirelength estimation, but such predictors are tied to circuit structure; other frameworks [24] neglect logic hierarchy and signal direction.The introduction identifies high-fidelity physical estimation for logic synthesis as an unresolved challenge because synthesis reshapes the logic network.Source: §1 · p. 1
- Integrated into ABC, LevelSyn replaces traditional heuristics with a physical-informed cost function that guides technology mapping toward netlists optimized for physical implementation.The framework uses DREAMPlace for physical design validation.Source: §1 · pp. 1–2
- LevelSyn achieves an average power reduction of 6.89% and timing delay reduction of 27.48%, with a 99.59% reduction in post-place-and-route DRC violations.The results are reported on the EPFL benchmark suite, with DRC validation after place and route.Source: §1 · pp. 1–2
- LA-GNN predicts AIG gate coordinates using hierarchical depth and directional signal flow, while LASP reduces memory overhead and preserves local logical dependencies.The model encodes pre-defined PI and PO constraints, produces row-consistent spatial priors, and derives cell orientation from predicted y-coordinates and PDK row specifications.Source: §1 · pp. 1–2
2 Related Works
Physical-aware synthesis research has sought to reunite logic optimization and placement as interconnect delays undermine logic-depth metrics. GNNs capture circuit structure and function, but practical physical synthesis still needs efficient, accurate spatial priors.
2.1 Evolution of Physical Aware Synthesis
- As interconnect delays came to dominate gate delays, logic-depth metrics became insufficient for timing closure in deep sub-micron design.Source: §2.1 · p. 2
- Gosti et al. interleaved logic operations with placement, while Maple integrated spatial information into technology mapping; complexity and inaccurate wire-load models limited early methods.OpenROAD improves integration infrastructure, but a unified metric remains challenging.Source: §2.1 · p. 2
- PigMap1 [24] used primitive-gate placement coordinates to guide mapping for performance or power, and PigMap2 added congestion-aware metrics, but placement inaccuracies limited mapping quality.The methods' spatial prior derives from fast placement engines, whose inaccurate coordinates create a fidelity gap.Source: §2.1 · p. 2
2.2 GNNs in EDA and Their Limitations
- DeepGate [17], DeepGate2 [29], FGNN [7], CircuitFusion [9], NetTAG [8], and Polargate learn circuit representations for functionality, classification, or multimodal data tasks.DeepGate uses attention and skip connections; DeepGate2 adds pairwise truth-table supervision and functionality-aware losses, while Polargate uses the bipolar principle.Source: §2.2 · p. 2
- Standard GNNs face memory and runtime costs on large netlists and do not directly provide spatial coordinates needed for physical optimization.Millions of gates can exceed standard GPU capacity, while inference latency may outweigh accuracy benefits in rapid synthesis iterations.Source: §2.2 · p. 2
3 Methodology · 3.1 Overview of the Proposed Framework
LevelSyn is an end-to-end physical-aware logic synthesis flow with three phases: hierarchical pre-processing, scalable spatial prediction, and physical-informed technology mapping. It uses AIG structure and fixed PI/PO floorplan constraints to predict internal-gate spatial information and guide mapping toward lower post-routing wirelength and delay.
3.1 Overview of the Proposed Framework
- LevelSyn has three phases: hierarchical pre-processing, scalable spatial prediction, and physical-informed technology mapping.The framework is presented as an end-to-end flow bridging logical abstraction and physical implementation.Source: §3.1 · p. 2, Figure 1 · p. 3
3.1.1 Problem Formulation.
- The input netlist is represented as a directed acyclic AIG of 2-input AND and inverter gates, with fixed PI/PO coordinates and orientations from the floorplan.These fixed boundary constraints are denoted C_fixed.Source: §3.1.1 · p. 2
- LevelSyn predicts spatial coordinates and orientations for every internal gate, using the fixed primary-input and primary-output constraints.The predicted quantities are (x_v, y_v, O_v) for gates outside PI ∪ PO.Source: §3.1.1 · p. 2
- The predicted coordinates are used to optimize technology mapping for lower post-routing wirelength and delay.This is the framework’s second stated objective.Source: §3.1.1 · p. 3
3.1.2 Framework Pipeline.
- Pre-processing extracts topological and hierarchical-level features, anchors the graph with fixed PI/PO coordinates, and partitions large designs into level-aligned subgraphs.The partitioning is intended to prevent memory overflow while maintaining logical continuity.Source: §3.1.2 · p. 3
- The Level-Asynchronous GNN propagates features along directional signal flow to capture the relationship between logic depth and physical placement.It processes partitioned AIG segments and outputs spatial-coordinate and orientation priors for every gate.Source: §3.1.2 · p. 3
- LevelSyn integrates the spatial priors into Berkeley ABC and extends the mapping cost function with wirelength-driven metrics for physical-aware gate-level optimization.The resulting netlist is intended to have superior PPA.Source: §3.1.2 · p. 3
3.2 Level-Aware GNN Architecture
LevelSyn’s Level-Aware GNN maps AIG structure to high-fidelity spatial priors while respecting the netlist’s directional signal flow and hierarchical levels.
3.2.1 Level-Asynchronous Message Passing.
- Nodes are leveled by maximum PI-to-node path length, and their features combine one-hot gate type, PI/PO coordinates, placeholder internal coordinates, fan-in/out degrees, and topological level.PI/PO coordinates are normalized to [0, 1], while internal gates start at the layout center (0.5, 0.5).Source: §3.2.1 · pp. 3–4
- The LA-GNN propagates information forward from fan-ins and backward from fan-outs so PI and PO spatial constraints guide internal-gate coordinate prediction.The forward pass follows topological order and the backward pass reverses it; fused directional representations support coordinate interpolation that respects the global floorplan.Source: §3.2.1 · p. 4
3.2.2 Orientation Estimation.
- Cell orientation is estimated from predicted y-position and floorplan row structure, alternating N and FS orientations on even and odd rows to keep spatial priors physically consistent.This supports synthesis-time estimates of pin locations and parasitic effects during mapping.Source: §3.2.2 · p. 4
3.3 Scalable Subgraph Partitioning
LevelSyn’s Level-Aligned Subgraph Partitioning (LASP) scales GNN processing by dividing AIGs into level-aligned subgraphs while preserving local logic dependencies. Global positional priors help independently processed subgraphs maintain a consistent coordinate system.
3.3 Scalable Subgraph Partitioning
- LASP partitions an AIG of maximum logic depth L into N contiguous segments along its hierarchical levels, unlike edge-cut methods [6, 15] that can disrupt topological flow.Each segment uses a level window of size w = ⌈L/N⌉.Source: §3.3 · p. 4
- Each level-aligned subgraph contains a complete logic slice, preserving local connectivity between adjacent levels for spatial proximity estimation.Source: §3.3 · p. 4
- LevelSyn injects a Normalized Level Index into initial node features so parallel subgraphs retain global position relative to PI and PO boundaries and spatial anchors.Source: §3.3 · p. 4
- LASP reduces each GNN pass’s memory complexity from O(|V|) to O(|V|/N), enabling LevelSyn to handle industrial benchmarks.The passage contrasts this with spectral-based methods that often incur cubic complexity from Laplacian eigen-decomposition.Source: §3.3 · p. 4
3.4 Physical-Aware Technology Mapping
LevelSyn integrates predicted AIG spatial priors into Berkeley ABC technology mapping, using wirelength-aware costs and iterative gate optimization to produce layout-friendly netlists.
3.4 Physical-Aware Technology Mapping
- LevelSyn extends ABC AIG nodes with predicted coordinates and orientations, then uses these physical attributes to estimate match wirelength before committing matches to the netlist.The physical attribute vector is P_v = (x̂_v, ŷ_v, Ô_v).Source: §3.4.1 · p. 4, §3.4 · p. 4
3.4.1 Physical Data Integration.
- LevelSyn augments technology-mapping cost with predicted wirelength, adapting its calculation to the optimization target in a strategy inspired by PigMAP [24].The cost is defined for each candidate match M implementing a set of AIG nodes, with weighting factors α, β, and γ.Source: §3.4.2 · p. 5
3.4.2 Wirelength-Driven Cost Function.
- For pwmap, LevelSyn sums Manhattan distances to adjacent pins to minimize total switching power, while pfmap uses the maximum distance to bound worst-case interconnect delay on critical paths.Both metrics use the predicted center of the candidate cell and its fan-in/fan-out neighbors.Source: §3.4.2 · p. 5
3.4.3 Mapping Execution and Optimization.
- The enhanced ABC flow evaluates library-cell matches with the augmented cost, favors matches that minimize net stretching relative to fixed PI/PO anchors, and iteratively swaps or sizes gates when equivalent cells better fit spatial priors without violating timing.These physical-informed mapping decisions are intended to reduce routing congestion and wire-induced delay in later physical-design stages.Source: §3.4.3 · p. 5
4 Experiments
Experiments evaluate LevelSyn on EPFL combinational circuits and report PPA, post-routing, runtime, and memory results across circuit scales.
4.1 Experimental Settings
- The evaluation uses EPFL circuits spanning hundreds to over 200,000 nodes, ABC synthesis and mapping, DREAMPlace coordinates, and the SkyWater standard-cell library.Baselines are ABC map and PigMap-power/performance; LA-GNN uses a 128-dimensional hidden layer, six message-passing layers, and 5,000-node partition windows.Source: §4.1 · p. 5
4.2 GNN Pre-training and Fine-tuning Results
- Pre-training on 500 to 10,000 randomly generated AIGs followed by circuit-specific fine-tuning accelerates convergence and improves predictive accuracy and robustness across circuit structures.The model is initialized with pre-trained weights and fine-tuned on benchmark circuits to adapt learned representations to realistic synthesis and physical-design constraints.Source: §4.2 · pp. 5–6
4.3 PPA Results
- LevelSyn-pwmap reduces average area by 6.52% and switching power by 6.89% versus PigMap-power, while its 27.48% delay reduction exceeds LevelSyn-pfmap’s 22.44%.The paper reports that LevelSyn outperforms the logic-only baseline and PigMap across the majority of test cases.Source: Table 1 · p. 6, §4.3 · p. 7
4.2 GNN Pre-training and Fine-tuning Results
- Across 700 epochs, level-asynchronous training converges to loss 0.61, below the synchronous GCN’s 0.75.Both methods reduce training loss rapidly at first, but level-asynchronous updating shows a sharper initial descent.Source: §4.2 · p. 6, Figure 4 · p. 7
- On hyp, with 214,591 nodes, LA-GNN predictions form a refined, high-density coordinate distribution, unlike the chaotic PigMap GiFt initialization.The resulting stable initial layout is presented as a useful starting point for downstream placement optimization and wirelength and timing convergence.Source: §4.2 · pp. 6–7, Figure 5 · p. 7
4.3 PPA Results
- After 20 routing iterations on Bar, LevelSyn-pwmap cuts total wire length by 20.66%, via counts by 28.36%, and DRC violations from 966 to 4 (99.59%).LevelSyn-pfmap reduces wire length by 19.32% and DRC violations by 97.27% versus its counterpart.Source: Table 2 · p. 7, §4.3 · p. 7
4.4 Runtime Analysis
- LevelSyn runtime remains competitive with PigMap; on multiplier and mem_ctrl it is comparable to or slightly lower, while sqrt and hyp mapping take relatively longer.The paper describes the additional latency on larger circuits as negligible within the full EDA flow, which includes subsequent placement and routing.Source: §4.4 · p. 7, Table 3 · p. 8
4.5 Ablation Study
- For hyp, partitioned LA-GNN uses 4,709 MB versus 8,956 MB for standard GCN, a 47.4% reduction, although LA-GNN uses slightly more memory on some smaller benchmarks.The authors attribute the large-circuit reduction to partitioning massive AIGs into subgraphs, avoiding storage of the full graph’s adjacency structure and gradient states.Source: Table 4 · p. 8, §4.5 · p. 8
5 Conclusion and Future Work
PhySyn embeds deep-learning spatial predictions into synthesis to bridge logic synthesis and physical implementation. It uses LA-GNN and level-aligned partitioning, with future work targeting sequential circuits and multi-objective optimization.
5 Conclusion and Future Work
- PhySyn combines LA-GNN spatial prediction with level-aligned partitioning to achieve high-fidelity spatial estimation and scalability for large-scale designs.The framework embeds deep-learning-based spatial predictions into the synthesis flow.Source: §5 · p. 8
- PhySyn’s near-total elimination of DRC violations highlights the potential of physical-aware synthesis for correct-by-construction design flows.Source: §5 · p. 8
- Future work will extend PhySyn to sequential circuits by incorporating flip-flop positioning and explore congestion and thermal distribution as multi-objective targets.Source: §5 · p. 8