Source-linked AI summary
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu
TL;DR
LevelSyn addresses the gap between logical synthesis and physical implementation by combining hierarchical spatial prediction with physical-informed synthesis. Its LA-GNN-based framework improves power, timing delay, and DRC outcomes on the EPFL benchmarks, while standard GNN deployment remains constrained by memory and runtime demands.
Problem
Existing physical-aware synthesis methods provide limited spatial fidelity, while large-scale GNN deployment faces memory and runtime bottlenecks.
Method
LevelSyn combines a level-asynchronous GNN that captures AIG signal flow and hierarchical depth with level-aligned partitioning and physical-informed technology mapping.
Results
LevelSyn achieves average power reduction of 6.89%, timing delay reduction of 27.48%, and DRC violation reduction of 99.59%.
Takeaways & Limitations
The framework provides high-fidelity spatial guidance and supports layout-friendly netlists and accelerated design convergence.
Takeaways & Limitations
Standard GNN-based approaches remain difficult to apply at industrial scale because million-gate netlists can exceed GPU memory and iterative convolutions add inference latency.
Abstract
from arXiv · showhide
As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies on non-physical Wire Load Models (WLMs), while recent spectral-based placement predictors often neglect the inherent hierarchical logic depth and signal flow of netlists, which leads to low-fidelity spatial estimations. To bridge this gap, we propose LevelSyn, a novel physical-aware logic synthesis framework that integrates hierarchical representation learning with a wirelength-driven optimization engine. At its core, LevelSyn leverages a level-asynchronous Graph Neural Network (GNN) to predict high-fidelity gate coordinates by capturing the structural and directional semantics of And-Inverter Graphs (AIGs). To handle industrial-scale designs, a level-aligned subgraph partitioning strategy is introduced to eliminate memory bottlenecks while preserving local logical dependencies. These spatial insights are seamlessly integrated into a newly developed physical-informed synthesis engine within the Berkeley ABC framework. Experimental results on the EPFL benchmark suite demonstrate that LevelSyn significantly outperforms state-of-the-art (SOTA) methods, achieving an average power reduction of 6.89\% and a timing delay improvement of 27.48\%. Furthermore, post-place-and-route validation shows a 99.59\% reduction in design rule check (DRC) violations, highlighting its effectiveness in accelerating design convergence.
1 Introduction
LevelSyn addresses the gap between logical synthesis and physical implementation by predicting spatial information from AIG structure and using it during technology mapping. Its physical-informed flow reports improved power, timing, and post-routing DRC outcomes.
- Motivation: Traditional logic synthesis estimates design quality from logical abstractions such as wire load models, limiting physical fidelity for modern designs.Physical-aware synthesis incorporates backend information earlier to estimate interconnect delay and congestion.
- Limitations of Prior Work: Existing GNN-based predictors estimate physical metrics but are tied to specific circuit structures that synthesis may later reshape.This limits their use mainly to minor refinement after synthesis.
- LevelSyn: LevelSyn uses a Level-Asynchronous GNN to capture AIG signal direction and hierarchical logic depth while a level-aligned partitioning strategy preserves local dependencies at scale.The framework targets industrial-scale designs by mitigating memory bottlenecks.
- LevelSyn: The framework predicts gate coordinates and row-consistent physical priors, deriving cell orientation and power-rail alignment from predicted y-coordinates.These priors provide physical guidance beyond spectral-based methods.
2 Related Works
Related work integrates physical information into synthesis but faces inaccurate spatial estimates, computational costs, and limitations in standard GNN representations. These gaps motivate more scalable models that directly provide physical priors.
- Physical-Aware Synthesis: Deep-submicron interconnect delays can dominate gate delays, making traditional logic-depth metrics insufficient for timing closure.Earlier integration methods also faced high complexity or inaccurate wire-load models.
- Physical-Aware Synthesis: PigMap methods use primitive-gate placement to guide technology mapping, but inaccurate fast-placement data can limit subsequent mapping quality.The reported fidelity gap prevents truly optimal results.
- GNNs in EDA: GNNs have been applied to learn structural and functional representations of combinational circuits, including through attention, skip connections, and truth-table supervision.These approaches primarily target logical functionality and representation learning.
- GNNs in EDA: Standard GNNs face memory consumption and inference-latency hurdles on large netlists, while lacking explicit spatial coordinates for physical optimization.The passage identifies a need for efficient architectures that directly provide accurate spatial priors.
3.1 Overview of the Proposed Framework
LevelSyn is an end-to-end flow that converts AIG structure and fixed I/O floorplan constraints into spatial priors, then uses those priors for physical-informed technology mapping. Its pipeline combines hierarchical preprocessing, scalable LA-GNN prediction, and wirelength-driven optimization.
- Framework Overview: LevelSyn comprises hierarchical preprocessing, scalable spatial prediction, and physical-informed technology mapping.The three phases form an end-to-end synthesis flow bridging logical abstraction and physical implementation.
- Problem Formulation: The AIG represents gates as nodes and signal flow as directed edges, while fixed PI/PO coordinates and orientations provide boundary constraints.The framework predicts coordinates and orientations for internal gates and uses them to optimize mapping.
- Hierarchical Pre-processing: Hierarchical preprocessing extracts topological and level information, encodes fixed I/O coordinates as spatial anchors, and partitions large graphs into manageable level-aligned segments.Partitioning prevents memory overflow while maintaining logical continuity.
- Scalable Spatial Prediction: The LA-GNN propagates features along directional signal flow across partitioned AIG segments and outputs spatial priors for every gate.This design captures correlations between logic depth and physical placement.
- Physical-Aware Technology Mapping: The predicted spatial priors are integrated into Berkeley ABC by extending the mapping cost function with wirelength-driven metrics.The resulting mapping makes physical-aware gate-level optimization choices aimed at superior PPA.
3.2 Level-Aware GNN Architecture
LevelSyn’s LA-GNN maps AIG structure to spatial priors while respecting hierarchical levels and directional signal flow. Bidirectional message passing combines PI-to-PO signal propagation with output-derived spatial constraints to predict physically consistent gate locations and orientations.
- LA-GNN maps AIG logical structure to high-fidelity spatial priors while respecting directional signal flow and hierarchical levels.
- AIG nodes are organized into sequential levels according to their maximum path length from any primary input.
- Node features combine gate type, spatial anchors, fan-in and fan-out degrees, and topological level information.
- Bidirectional level-asynchronous message passing propagates features forward from primary inputs and backward from primary outputs.The two passes allow internal gates to receive constraints from both PI and PO anchors.
- The final embedding fuses forward and backward states so downstream coordinate regression respects the global floorplan.
- Predicted y-coordinates are converted into discrete standard-cell rows, whose parity determines the estimated cell orientation.The row mapping uses the standard-cell row height and layout boundary offset.
3.3 Scalable Subgraph Partitioning
LevelSyn uses level-aligned subgraphs to scale spatial prediction while preserving local logic structure. Global positional priors and normalized level information maintain coordinate consistency across parallel subgraph processing.
- Level-Aligned Subgraph Partitioning scales LevelSyn while preserving directional logic dependencies.
- The strategy divides an AIG into contiguous segments along hierarchical levels rather than minimizing edge cuts alone.
- Each subgraph contains a complete logic slice, maintaining connectivity between adjacent levels for spatial proximity estimation.
- Global positional priors are injected into initial node features so independently processed subgraphs retain global coordinate information.
- The Normalized Level Index lets parallel GPU batches perceive relative distance between primary-input and primary-output boundaries.
- Memory complexity per GNN pass decreases from O(|V|) to O(|V|/N), capping peak memory as circuit size grows.
3.4 Physical-Aware Technology Mapping
LevelSyn integrates predicted spatial coordinates and orientations into Berkeley ABC’s technology mapping flow. Its physical-informed mapper evaluates candidate matches with wirelength-aware costs and refines cells toward spatially compatible implementations.
- The mapping flow integrates predicted spatial priors into Berkeley ABC to connect logical optimization with physical layout requirements.
- Predicted coordinates and orientations are back-annotated into ABC nodes as physical attributes for mapping decisions.
- LevelSyn augments standard mapping commands with a cost function combining area, delay, and predicted wirelength.
- Predicted wirelength uses Manhattan distance between candidate-cell centers and neighboring fan-in or fan-out pins.
- Power-oriented mapping sums Manhattan distances to adjacent pins, whereas delay-oriented mapping uses the maximum distance to bound critical-path interconnect delay.
- An iterative refinement stage swaps or sizes functionally equivalent cells when they better fit spatial priors without violating timing constraints.
4 Experiments
LevelSyn is evaluated across EPFL benchmarks and physical-design validation using LA-GNN pre-training, spatial prediction, and physical-aware mapping variants. It improves PPA, routing outcomes, convergence behavior, and large-design memory scalability relative to the reported baselines.
- Experimental Setup: The evaluation uses EPFL combinational benchmarks spanning hundreds to over 200k nodes, with Berkeley ABC, DREAMPlace, and the SkyWater standard-cell library.The study compares industry-standard and state-of-the-art physical-aware synthesis baselines.
- GNN Pre-training and Fine-tuning Results: LA-GNN is pre-trained on randomly generated AIGs and then fine-tuned on benchmark circuits to improve predictive accuracy and robustness across structural variations.The training strategy uses large-scale pre-training followed by task-specific fine-tuning.
- GNN Pre-training and Fine-tuning Results: 0.61 final training loss is achieved by level-asynchronous updating, compared with 0.75 for the synchronous 5-layer GCN over 700 epochs.Both approaches reduce loss rapidly initially, but level-asynchronous updating follows a sharper descent and reaches the lower loss.
- GNN Pre-training and Fine-tuning Results: On hyp, which contains 214,591 nodes, LA-GNN predictions form a refined high-density coordinate manifold, unlike the chaotic PigMap GiFt initialization distribution.The scatter comparison is made against true ground-truth placements.
- PPA Results: 6.89% switching power improvement and 6.52% area reduction are achieved by LevelSyn-pwmap versus PigMap-power, while LevelSyn-pwmap also delivers the best overall delay reduction of 27.48%.LevelSyn-pfmap reduces delay by 22.44% through critical-path-oriented optimization.
- Post-Routing Results: 99.59% fewer DRC violations are reported for LevelSyn-pwmap than PigMap-power on Bar, alongside 20.66% shorter total wire length and 28.36% fewer vias under the same 20 routing iterations.LevelSyn-pfmap achieves 19.32% wire-length improvement and 97.27% DRC reduction in the same case study.
- Ablation Study: 4,709 MB versus 8,956 MB is allocated on hyp for LAGNN and GCN, respectively, corresponding to an approximately 47.4% memory reduction enabled by LASP.LA-GNN has higher inherent memory overhead than standard GCN on smaller benchmarks, but LASP mitigates this overhead at large scale.
5 Conclusion and Future Work
PhySyn bridges logic synthesis and physical implementation by embedding deep-learning spatial predictions into synthesis, using LA-GNN and level-aligned partitioning for scalable, high-fidelity estimation. Its near-total DRC reduction supports correct-by-construction design flows, while future work targets sequential circuits and additional physical objectives.
- PhySyn embeds deep-learning spatial predictions into the synthesis flow to bridge logic synthesis and physical implementation.
- LA-GNN and level-aligned partitioning provide high-fidelity spatial estimation and scalability for large-scale designs.
- Near-total elimination of DRC violations underscores the potential of physical-aware synthesis for correct-by-construction design flows.
- Future work will extend the framework to sequential circuits with flip-flop positioning and explore congestion and thermal-distribution objectives.
- The paper is titled LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks.