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NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph

Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie

arXiv:2504.09260v1cs.ARcs.LG

TL;DR

Existing circuit representation methods rely on task-specific supervision or miss either netlist semantics or structure. NetTAG combines gate attributes and graph structure, and outperforms task-specific models across four functional and physical EDA tasks.

  • Problem

    Task-specific circuit models require extensive labels and customization, while LLMs struggle with flattened netlists and structural encoding.

    Source: §I · p. 1

  • Method

    NetTAG represents netlists as text-attributed graphs with gate logic and physical attributes, then combines an LLM text encoder with a graph transformer and cross-stage pre-training alignment.

    Source: §I · pp. 1–2

  • Results

    Across four EDA tasks, NetTAG outperforms all state-of-the-art task-specific models, with 14% higher accuracy in logic gate identification.

    Source: §I · p. 2

  • Takeaways & Limitations

    NetTAG supports diverse gate types and functional and physical tasks through a shared netlist representation-learning model.

    Source: §V · p. 6

Abstract

from arXiv · show

Circuit representation learning has shown promise in advancing Electronic Design Automation (EDA) by capturing structural and functional circuit properties for various tasks. Existing pre-trained solutions rely on graph learning with complex functional supervision, such as truth table simulation. However, they only handle simple and-inverter graphs (AIGs), struggling to fully encode other complex gate functionalities. While large language models (LLMs) excel at functional understanding, they lack the structural awareness for flattened netlists. To advance netlist representation learning, we present NetTAG, a netlist foundation model that fuses gate semantics with graph structure, handling diverse gate types and supporting a variety of functional and physical tasks. Moving beyond existing graph-only methods, NetTAG formulates netlists as text-attributed graphs, with gates annotated by symbolic logic expressions and physical characteristics as text attributes. Its multimodal architecture combines an LLM-based text encoder for gate semantics and a graph transformer for global structure. Pre-trained with gate and graph self-supervised objectives and aligned with RTL and layout stages, NetTAG captures comprehensive circuit intrinsics. Experimental results show that NetTAG consistently outperforms each task-specific method on four largely different functional and physical tasks and surpasses state-of-the-art AIG encoders, demonstrating its versatility.

I. INTRODUCTION

Existing circuit encoders and LLMs each leave gaps in representing diverse netlists. NetTAG combines gate semantics with graph structure and reports gains across functional and physical EDA tasks.

I. INTRODUCTION

  • Existing task-specific supervised methods require extensive labels and customization, are time-consuming to develop, and often capture task-specific rather than generalizable circuit patterns.Source: §I · p. 1
  • Graph-only encoders prioritize structure, often target AIGs, and lack physical information; truth-table supervision also faces exponential state expansion for complex post-synthesis gates.These limits constrain their applicability to post-mapping tasks, especially those evaluating physical design quality.Source: §I · p. 1
  • LLMs capture textual semantics but struggle to interpret flattened gate-level netlists and encode their circuit structures.Source: §I · p. 1
  • NetTAG represents gates with symbolic logic expressions and physical characteristics as text attributes, combining gate semantics with global graph structure.Its ExprLLM encodes gate attributes, then TAGFormer refines those embeddings with graph structure.Source: §I · pp. 1–2
  • NetTAG outperforms all state-of-the-art task-specific models across four EDA tasks, with 14% higher accuracy in logic gate identification.The reported results also include 13% higher accuracy in register function identification, 2% lower register slack error, and 7% lower circuit area and power prediction errors.Source: §I · p. 2

II. METHODOLOGY

NetTAG’s workflow converts sequential circuits into register-cone text-attributed graphs, then pre-trains and aligns their embeddings for downstream tasks. The representation combines gate logic and physical attributes with graph connectivity.

B. Circuit Data Preprocessing

  • Each gate becomes a graph node with a token-sequence attribute containing functional and physical properties, while edges connect gates.Source: B. Circuit Data Preprocessing · p. 2
  • Gate functionality is represented by symbolic Boolean expressions derived from each gate’s k-hop fan-in cone.The expressions are constructed using a formal verification toolkit.Source: B. Circuit Data Preprocessing · p. 2

A. Overview

  • Sequential netlists are chunked into combinational register cones, converted to text-attributed graphs, pre-trained with node- and graph-level objectives, aligned with RTL and layout embeddings, then fine-tuned for tasks.Source: Figure 2 · p. 2, A. Overview · p. 2

B. Circuit Data Preprocessing

  • Boolean expressions represent diverse gate types, while physical attributes include standard-cell characteristics such as power, area, delay, toggle rate, load, capacitance, and resistance.The paper states that symbolic expressions support static functional analysis without exhaustive truth-table simulation’s exponential growth.Source: B. Circuit Data Preprocessing · p. 2
  • RTL is processed as text, netlists as text-attributed graphs, and layout as connectivity graphs annotated with physical information from SPEF.The netlist’s symbolic expressions are derived from k-hop input cones; the figure identifies gate name, type, expression, and physical property as node attributes.Source: B. Circuit Data Preprocessing · pp. 2–3, Figure 3 · p. 3
  • For scalability, the method backtraces each register’s driving logic to other registers, creating a cone that captures its state transition and timing paths.The same chunking is applied to netlist, RTL, and layout data so corresponding cones remain functionally equivalent for alignment.Source: B. Circuit Data Preprocessing · p. 3

C. NetTAG Model Architecture

NetTAG encodes gate text attributes with ExprLLM, then uses TAGFormer to refine node representations with netlist structure. Auxiliary RTL and layout encoders provide embeddings for cross-stage alignment during pre-training.

C. NetTAG Model Architecture

  • During pre-training, auxiliary RTL and layout encoders generate embeddings for cross-stage alignment; these encoders are used only in pre-training.Source: C. NetTAG Model Architecture · p. 3
  • ExprLLM uses an LLM-based text embedding model to encode each gate’s text attributes as an initial text embedding.The decoder-only LLM is adapted by converting causal attention to bidirectional attention.Source: C. NetTAG Model Architecture · p. 3
  • TAGFormer concatenates each gate’s text embedding with its physical-characteristics vector, then processes gate nodes and connectivity to produce gate and graph embeddings.A [CLS] node connected to all other nodes serves as the graph-level embedding.Source: C. NetTAG Model Architecture · p. 3

D. Pre-Training Step 1: Enhacing logic understanding in ExprLLM

Pre-training first strengthens ExprLLM’s understanding of Boolean expressions, then trains TAGFormer to fuse frozen gate semantics with netlist structure through gate- and graph-level objectives.

D. Pre-Training Step 1: Enhacing logic understanding in ExprLLM

1) Pre-training within TAGFormer for semantic and structure fusion:

  • TAGFormer’s masked-gate reconstruction predicts masked gate types from the remaining graph nodes, using connectivity to capture structural roles.The objective treats gate type as a multi-class classification target and uses cross-entropy loss.Source: 1) Pre-training within TAGFormer for… · p. 3
  • Netlist graph contrastive learning brings positive netlist pairs closer while separating them from negative samples in the batch.Positive samples come from functionally equivalent netlist transformations.Source: 1) Pre-training within TAGFormer for… · pp. 3–4

D. Pre-Training Step 1: Enhacing logic understanding in ExprLLM

  • The workflow freezes ExprLLM before training TAGFormer to fuse gate semantics with global graph structure, then aligns NetTAG embeddings with pre-trained RTL and layout encoders.The passage notes that most registers remain unchanged across design stages.Source: D. Pre-Training Step 1: Enhacing logic… · p. 3, Figure 4 · p. 4

1) Pre-training within TAGFormer for semantic and structure fusion:

  • Graph-size prediction regresses the count of each gate type from the graph-level embedding, minimizing mean squared error against the actual counts.An auxiliary regression model takes the graph-level embedding as input.Source: 1) Pre-training within TAGFormer for… · p. 4

2) Pre-training beyond TAGFormer to enhance functional and physical awareness:

NetTAG adds cross-stage contrastive alignment, placing RTL, netlist, and layout circuit embeddings in a shared latent space.

2) Pre-training beyond TAGFormer to enhance functional and physical awareness:

  • Cross-stage contrastive learning aligns RTL, netlist, and layout circuit embeddings in a shared latent space, integrating RTL functionality and layout implementation into NetTAG.The paper states that this alignment enhances cross-stage awareness for functional and physical downstream tasks.Source: 2) Pre-training beyond TAGFormer to… · p. 4

F. Fine-tuning for downstream tasks

NetTAG produces embeddings at gate, register-cone, and full-circuit granularities, then fine-tunes them with lightweight models for functional and physical tasks.

F. Fine-tuning for downstream tasks

  • NetTAG generates embeddings for combinational gates, register cones, and entire circuits; sequential-circuit embeddings sum register-cone embeddings, while combinational circuits use the [CLS] node.Combinational circuits do not need to be chunked into cones for their circuit-level embedding.Source: F. Fine-tuning for downstream tasks · p. 4
  • Lightweight models such as MLPs or XGBoost fine-tune NetTAG embeddings for regression and classification across functional and physical netlist tasks.Functional predictions include gate functions and register types; physical predictions include register endpoint slack, power, and area.Source: F. Fine-tuning for downstream tasks · p. 4

A. Experimental Setup

NetTAG is evaluated on four functional and physical netlist tasks across different circuit granularities, using open-source designs and benchmarks. It outperforms task-specific baselines on each task, with reported gains in gate identification, register classification, slack prediction, and circuit power and area estimation.

A. Experimental Setup

  • Pre-training data includes 626k augmented expressions, 200k augmented subcircuit cones, and 10k aligned RTL and layout cones; circuits were synthesized and physically designed using commercial tools.The source RTL designs include ITC99, OpenCores, Chipyard, and VexRiscv.Source: A. Experimental Setup · p. 4, Table II · p. 4

B. Performance on Various Downstream Tasks

C. Comparision with pre-trained netlist encoders

On an AIG-format dataset, NetTAG surpasses state-of-the-art pre-trained AIG encoders across metrics. The comparison also evaluates standalone ExprLLM and notes that existing encoders are limited to combinational AIG circuits.

C. Comparision with pre-trained netlist encoders

  • On the AIG dataset, NetTAG achieves the highest average performance across metrics, outperforming FGNN and DeepGate3.The comparison is restricted to Task 1 because the other pre-trained netlist encoders are limited to combinational AIG circuits.Source: C. Comparision with pre-trained… · p. 5, Figure 5 · p. 5
  • Standalone ExprLLM also performs well using symbolic expressions, highlighting gate-semantic understanding in the comparison.The paper describes NetTAG’s advantage as combining semantic and structural information through TAG.Source: C. Comparision with pre-trained… · p. 5
  • NetTAG’s accuracy on the AIG dataset is reported as superior to its accuracy on the more diverse gate datasets used for Task 1 in TABLE III.This comparison is stated as evidence of adaptability.Source: C. Comparision with pre-trained… · p. 5

D. Ablation Study

The ablations associate TAG attributes, self-supervised objectives, and cross-stage alignment with performance gains across functional and physical tasks. Runtime analysis reports an approximately 10x speedup over traditional commercial-EDA physical-design workflows.

D. Ablation Study

  • Removing TAG text attributes significantly reduces functional-task performance and slightly lowers physical-task performance.The authors interpret this as evidence that semantic attributes matter especially for functional tasks, while also benefiting structure-focused tasks.Source: D. Ablation Study · p. 6
  • Expression contrastive learning (#1) has the greatest impact on functional tasks; masked gate reconstruction (#2.1) and graph contrastive learning (#2.2) improve both task types.Graph size prediction (#2.3) has its strongest effect on physical tasks.Source: D. Ablation Study · p. 6
  • Removing cross-stage alignment causes a notable performance drop across all four tasks.The paper says alignment strengthens integration of early-stage functional and late-stage physical information.Source: D. Ablation Study · p. 6

E. Runtime Analysis

  • Runtime is about 10x faster than traditional physical-design workflows using commercial EDA tools, with preprocessing and ExprLLM node inference consuming most of NetTAG’s runtime.The paper identifies parallel expression extraction and additional GPU resources as possible routes to reducing runtime.Source: E. Runtime Analysis · p. 6

A. Scalability: Performance Scaling with Model and Data Size

NetTAG’s downstream performance improves with larger ExprLLM backbones and more pre-training data. A demo shows improved arithmetic-function interpretation when NetTAG gate-function identification is supplied to an LLM; the conclusion proposes larger pre-training datasets and decoding methods as future work.

A. Scalability: Performance Scaling with Model and Data Size

B. Demo: Reasoning Netlist’s Arithmetic Function with NetTAG

  • With NetTAG gate-function identification, an LLM correctly interprets a flattened arithmetic netlist as comparing two 2-bit values, performing addition and multiplication, then selecting a result.Without NetTAG, the LLM struggles to interpret the netlist’s functionality.Source: Figure 8 · p. 6, B. Demo: Reasoning Netlist’s… · p. 6

V. CONCLUSION AND FUTURE WORK

  • NetTAG supports diverse gate types and functional and physical tasks; future work will expand pre-training to larger circuit datasets and explore decoding methods to broaden task support.The paper’s conclusion describes NetTAG as a foundation model for netlist representation learning.Source: §V · p. 6

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