CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis

• DNNs perform billions or trillions of MAC operations, creating high hardware costs.Source: §1 · p. 1
• Approximate computing reduces hardware costs by exploiting the error tolerance of AI workloads.Source: §1 · p. 1
• Conventional approximate circuits typically target a single fixed accuracy–efficiency operating point.Source: §1 · p. 1
• Error tolerance varies across workloads, layers, and channels, creating demand for runtime support of multiple error levels.Source: §1 · p. 1
• Evolutionary algorithms, including genetic algorithms and cartesian genetic programming, suit approximate-circuit design because they explore discrete and non-differentiable design spaces.Source: §1 · p. 1

• A single netlist must satisfy multiple mode-specific error constraints for runtime-selectable accuracy.Source: √Multi-Threshold Verifiability Miter · p. 1
• CircuitsDNA automatically generates accuracy-configurable arithmetic circuits by combining multi-constraint evolution, shared-logic exploration, nonstalling verification, and adaptive mutation.Source: √Multi-Threshold Verifiability Miter · p. 1
• The unified miter encodes multiple accuracy thresholds in one formal-verification instance, avoiding separate mode-specific verification and hardware implementations.Source: √Multi-Threshold Verifiability Miter · p. 1
• RVS bounds SAT verification time and asynchronously handles over-budget candidates, decoupling costly verification from the main search while preserving exact correctness guarantees.Source: √Multi-Threshold Verifiability Miter · p. 1
• Adaptive mutation adjusts operator probabilities according to mutation effectiveness and improves search convergence speed by up to 33% with negligible overhead.Source: √Multi-Threshold Verifiability Miter · p. 2

• Quantization and mixed-precision computing reduce costs by selecting predefined bit widths, limiting the explored discrete design space.Source: §2 · p. 2
• Logic-level approximate adders and multipliers broaden PPA-error trade-offs, but most provide only one fixed accuracy-efficiency operating point.Source: §2 · p. 2
• Existing automated and runtime-configurable synthesis approaches still rely on predefined decomposition or configuration structures.Source: §2 · p. 2
• Automatically evolving circuits for multiple runtime-selectable accuracy modes under independent worst-case error constraints remains underexplored.Source: §2 · p. 2
• CircuitsDNA unifies precision adaptation, runtime configurability, and constrained circuit optimization through shared hardware resources, adaptive mutation, and nonstalling formal verification.Source: §2 · p. 2

3 CircuitsDNA Framework

• Adaptive mutation generates structurally modified circuits, while a lightweight proxy filter removes candidates unlikely to improve the current solution.Source: §3 · p. 2
• The multi-threshold miter compares candidate and golden circuits against all mode-specific error thresholds within one verification instance.Source: §3 · p. 2
• RVS uses time-bounded SAT verification for easy cases and transfers timed-out candidates off the main search path.Source: §3 · p. 2

3.1.1 Circuit Representation and Optimization Objective.

• Candidates are represented as directed acyclic graphs whose nodes implement primitive gates and whose edges encode signal dependencies.Source: §3.1 · p. 2
• The search minimizes circuit area, defined as the sum of gate-dependent node areas, subject to mode-specific accuracy constraints.Source: §3.1.1 · p. 3
• For an 8-bit two’s-complement signed multiplier, maximum golden-output magnitude is 16384, so WCE 128 equals normalized WCE 0.78%.Source: §3.1.1 · p. 3

3.1.2 Structural Mutation Operators.

• Six mutation operators modify topology, gate type, equivalence, inputs, or outputs to generate new candidate circuits.Source: §3.1.2 · p. 3
• Credit-driven EWA updates mutation probabilities after verified improvements, while a floor prevents permanent suppression of any operator.Source: §3.1.2 · p. 3

Candidate Filtering

• Area-based proxy filtering sends only candidates that improve the current best area to formal verification.Candidates failing the filter bypass formal verification and receive a fitness penalty.Source: §3.2 · p. 3

Multi-Threshold Miter

• The multi-threshold miter computes candidate error against a golden circuit and checks mode-specific thresholds selected by the configuration signal.A sign-aware comparison module evaluates error magnitude, producing one violation output across modes.Source: §3.2.1 · p. 3

Bounded Verification

• Resource-limited verifiability-driven search processes the unified miter under a bounded verification budget.Candidates resolved within budget proceed to fitness evaluation, while timed-out candidates leave the critical search path.Source: §3.3 · p. 3

Asynchronous Fallback Verification

• Asynchronous exhaustive verification handles SAT timeouts in a separate parallel queue and reinjects pass/fail results into fitness evaluation.This prevents difficult candidates from stalling the evolutionary loop before ranking and environmental selection.Source: §3.3.1 · p. 3

PPA-Accuracy Trade-offs

• The exact multiplier occupies 207.4 μm2 with a 0.70-ns delay.Source: §4.1.2 · p. 4
• 56% reduction: M2,5 reaches normalized AP 0.44 in CFG@ under the ResNet-20 workload.Its area is 151.7 μm2, 27% below the exact baseline, with lower switching supplying the remaining gain.Source: §4.1.2 · p. 4
• 93% maximum AP reduction occurs under exhaustive stimulation, while the workload-based 56% result is more deployment-relevant.Changing CFG@[00] to CFG@ lowers AP by 10-17% under the real workload.Source: §4.1.2 · p. 4

Constraint Satisfaction

• Every selected design satisfies all four WCE constraints across repeated runs.Some modes retain slack because WCE is a feasibility constraint, while all modes compete for the same logic.Source: §4.1.3 · p. 4

Area Variation

• Seven of nine selected variants are smaller than the exact baseline.M1,1 and M2,1 remain slightly larger because CFG@[00] is bit-exact while multi-mode control remains present.Source: §4.1.3 · p. 4

RVS Ablation

• At 16 bits, SAT-only passes nothing at 0.5 s while RVS still progresses.RVS moves unresolved candidates off the critical path, and its advantage disappears when the SAT limit is long enough to resolve candidates in-loop.Source: §4.1.4 · p. 4
• 81-87% of verified passes come from fewer than 1% of fallback calls at 0.05-0.2 s.Fallback pass rate rises from 26% to 95% as the SAT limit increases, then fallback stops firing at 0.5 s.Source: §4.1.4 · p. 4

Adaptive-Mutation Ablation

• 1.33× faster convergence: EWA α=0.05 reaches the 50% area target than fixed mutation.A larger α=0.20 gives the largest near-final 90% speedup of 1.32×.Source: §4.1.5 · p. 5

• A shared 2-bit register enables offline per-layer mode selection without changing the systolic-array datapath.Source: §4.2 · p. 6
• 10–21% energy savings are achieved by approximate modes, which consume 6.8 × 10−2 to 7.7 × 10−2 pJ per multiplication versus 8.56 × 10−2 pJ for the exact unit.Source: §4.2 · p. 6
• LeNet-5 and ResNet-20 tolerate 5.5% WCE with accuracy losses of 0.10 and 1.48 percentage points relative to FP32.Source: §4.2 · p. 6
• ResNet-18 tolerates 1% WCE with a 1.09-point loss, while ResNet-50 incurs a 1.36-point loss at 0.1% WCE.Source: §4.2 · p. 6
• DeiT-Tiny and DeiT-Small lose 1.9–2.0 points at 1% WCE, indicating applicability beyond CNNs but a preference for tighter modes.Source: §4.2 · p. 6

• The 12- and 16-bit experiments use 20 and 3 seeds, respectively, with population size 2 and only the highest-accuracy mode.Source: §4.3 · p. 6
• Relaxing the WCE budget exposes lower-AP circuits across the evaluated multiplier widths.Source: §4.3 · p. 6, Figure 8 · p. 6
• Search completes in approximately 2 hours at 12 bits and 5 hours at 16 bits despite harder verification.Source: §4.3 · p. 6
• The 16-bit experiment demonstrates feasibility beyond INT8 rather than providing a statistically matched cross-width PPA comparison.Source: §4.3 · p. 6

• Existing automated methods generally generate separate fixed-accuracy circuits, whereas runtime-configurable designs often rely on predefined approximation structures.Source: §4.4 · p. 6
• Because prior works use different technologies, workloads, and error metrics, the comparison emphasizes capability coverage rather than numerical PPA results.Source: §4.4 · p. 6

• Up to 56% area-power-product reduction is reported on the ResNet-20 INT8 workload, and 93% under exhaustive activity, relative to an exact multiplier.Source: §5 · p. 6
• Across evaluated CNNs and DeiTs, accuracy loss relative to FP32 remains below 2% after fine-tuning under WCE budgets of ≤1%.Source: §5 · p. 6
• RVS eliminates search stalls observed with synchronous verification across 8-, 12-, and 16-bit multipliers.Source: §5 · p. 6
• Adaptive mutation accelerates convergence by up to 1.33× without relying on predefined approximation structures.Source: §5 · p. 6