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CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Ruichen Qi, Junyi Luo, Xinting Jiang, Quan Cheng, Gregory Kielian, Ben Laurie, Dennis Sylvester, Mehdi Saligane
TL;DR
Existing approximate circuits are usually fixed-accuracy or depend on predefined runtime-configurable structures, while edge AI needs adjustable accuracy-efficiency trade-offs. CircuitsDNA evolves a single multi-mode arithmetic circuit using unified verification, resource-limited search, and adaptive mutation. Its evaluated multipliers reduce area-power product substantially, preserve low fine-tuned accuracy loss, avoid observed search stalls, and accelerate convergence.
Problem
Existing approximate circuits are typically fixed-accuracy or rely on predefined structures, limiting runtime-selectable accuracy under varying workload requirements.
Method
CircuitsDNA evolves unified accuracy-configurable arithmetic circuits using a multi-threshold verifiability miter, resource-limited verifiability-driven search, and feedback-driven adaptive mutation.
Results
8-bit multiplier variants reduce area-power product by up to 56% on ResNet-20 INT8 workload and 93% under exhaustive activity relative to an exact multiplier, while accuracy loss remains below 2% after fine-tuning.
Takeaways & Limitations
CircuitsDNA eliminates observed search stalls across 8-, 12-, and 16-bit multipliers, and adaptive mutation accelerates convergence by up to 1.33×.
Abstract
from arXiv · showhide
Emerging edge AI workloads increasingly require arithmetic units that can trade computational accuracy for efficiency on demand. However, existing approximate arithmetic circuits are typically fixed-accuracy or rely on predefined structures for runtime configurability. This work introduces CircuitsDNA, an evolutionary framework that automatically evolves accuracy-configurable arithmetic circuits supporting multiple accuracy modes within a single circuit. It integrates three key features: 1) multi-threshold verifiability miter to enforce mode-specific accuracy requirements, 2) resource-limited verifiability-driven search to reduce verification overhead without sacrificing correctness, enabling efficient exploration of large circuit design, and 3) feedback-driven adaptive mutation to prioritize effective structural modifications and accelerate search convergence. Experimental results show that the 8-bit multiplier variants synthesized in 28-nm CMOS reduce the area-power product by up to 56% on INT8 DNN workload and 93% under exhaustive activity, compared with an exact 8-bit multiplier. Across CNNs and DeiTs, the accuracy loss relative to FP32 remains below 2% after fine-tuning under worst-case error (WCE) budgets of at most 1%. CircuitsDNA eliminates all search stalls observed in conventional methods across 8/12/16-bit multipliers, while adaptive mutation provides up to 1.33 times faster convergence than its non-adaptive counterpart.
1 Introduction
DNN computation creates high hardware costs, motivating approximate circuits that exploit workload error tolerance. Existing approaches generally provide fixed accuracy, despite runtime-varying error tolerance across workloads, layers, and channels.
- DNNs perform billions or trillions of MAC operations, creating high hardware costs.
- Approximate computing reduces hardware costs by exploiting the error tolerance of AI workloads.
- Conventional approximate circuits typically target a single fixed accuracy–efficiency operating point.
- Error tolerance varies across workloads, layers, and channels, creating demand for runtime support of multiple error levels.
- Evolutionary algorithms, including genetic algorithms and cartesian genetic programming, suit approximate-circuit design because they explore discrete and non-differentiable design spaces.
√Multi-Threshold Verifiability Miter
CircuitsDNA combines unified multi-threshold verification, resource-limited search, and feedback-driven mutation to evolve one circuit supporting multiple runtime accuracy modes. These mechanisms address simultaneous mode constraints, verification stalls, and inefficient static mutation policies.
- A single netlist must satisfy multiple mode-specific error constraints for runtime-selectable accuracy.
- CircuitsDNA automatically generates accuracy-configurable arithmetic circuits by combining multi-constraint evolution, shared-logic exploration, nonstalling verification, and adaptive mutation.
- The unified miter encodes multiple accuracy thresholds in one formal-verification instance, avoiding separate mode-specific verification and hardware implementations.
- RVS bounds SAT verification time and asynchronously handles over-budget candidates, decoupling costly verification from the main search while preserving exact correctness guarantees.
- Adaptive mutation adjusts operator probabilities according to mutation effectiveness and improves search convergence speed by up to 33% with negligible overhead.
2 Related Work
Prior work separately addresses precision adaptation, runtime configurability, and constrained circuit optimization, but leaves automatic evolution of shared multi-mode circuits under independent WCE constraints underexplored. CircuitsDNA unifies these directions.
- Quantization and mixed-precision computing reduce costs by selecting predefined bit widths, limiting the explored discrete design space.
- Logic-level approximate adders and multipliers broaden PPA-error trade-offs, but most provide only one fixed accuracy-efficiency operating point.
- Existing automated and runtime-configurable synthesis approaches still rely on predefined decomposition or configuration structures.
- Automatically evolving circuits for multiple runtime-selectable accuracy modes under independent worst-case error constraints remains underexplored.
- CircuitsDNA unifies precision adaptation, runtime configurability, and constrained circuit optimization through shared hardware resources, adaptive mutation, and nonstalling formal verification.
3 CircuitsDNA Framework
CircuitsDNA evolves a single multi-mode circuit through adaptive mutation, proxy filtering, unified threshold verification, and resource-limited search. It represents candidates as gate-level DAGs and optimizes area subject to mode-specific WCE budgets.
- 3 CircuitsDNA Framework: Adaptive mutation generates structurally modified circuits, while a lightweight proxy filter removes candidates unlikely to improve the current solution.
- 3 CircuitsDNA Framework: The multi-threshold miter compares candidate and golden circuits against all mode-specific error thresholds within one verification instance.
- 3 CircuitsDNA Framework: RVS uses time-bounded SAT verification for easy cases and transfers timed-out candidates off the main search path.
- 3.1.1 Circuit Representation and Optimization Objective.: Candidates are represented as directed acyclic graphs whose nodes implement primitive gates and whose edges encode signal dependencies.
- 3.1.1 Circuit Representation and Optimization Objective.: The search minimizes circuit area, defined as the sum of gate-dependent node areas, subject to mode-specific accuracy constraints.
- 3.1.1 Circuit Representation and Optimization Objective.: For an 8-bit two’s-complement signed multiplier, maximum golden-output magnitude is 16384, so WCE 128 equals normalized WCE 0.78%.
- 3.1.2 Structural Mutation Operators.: Six mutation operators modify topology, gate type, equivalence, inputs, or outputs to generate new candidate circuits.
- 3.1.2 Structural Mutation Operators.: Credit-driven EWA updates mutation probabilities after verified improvements, while a floor prevents permanent suppression of any operator.
3.2 Multi-Threshold Verifiability Miter
CircuitsDNA filters and verifies candidate circuits against mode-specific accuracy thresholds while limiting verification cost. Resource-bounded verification and asynchronous fallback keep unresolved candidates from stalling the evolutionary search.
- Candidate Filtering: Area-based proxy filtering sends only candidates that improve the current best area to formal verification.Candidates failing the filter bypass formal verification and receive a fitness penalty.
- Multi-Threshold Miter: The multi-threshold miter computes candidate error against a golden circuit and checks mode-specific thresholds selected by the configuration signal.A sign-aware comparison module evaluates error magnitude, producing one violation output across modes.
- Bounded Verification: Resource-limited verifiability-driven search processes the unified miter under a bounded verification budget.Candidates resolved within budget proceed to fitness evaluation, while timed-out candidates leave the critical search path.
- Asynchronous Fallback Verification: Asynchronous exhaustive verification handles SAT timeouts in a separate parallel queue and reinjects pass/fail results into fitness evaluation.This prevents difficult candidates from stalling the evolutionary loop before ranking and environmental selection.
4.1 Configurable Signed Multiplier Synthesis
CircuitsDNA synthesizes configurable signed multipliers whose shared hardware supports multiple accuracy modes, with relaxed error budgets exposing lower-cost designs. Resource-limited verification and adaptive mutation improve exploration across repeated evolutionary runs.
- PPA-Accuracy Trade-offs: The exact multiplier occupies 207.4 μm2 with a 0.70-ns delay.
- PPA-Accuracy Trade-offs: 56% reduction: M2,5 reaches normalized AP 0.44 in CFG@ under the ResNet-20 workload.Its area is 151.7 μm2, 27% below the exact baseline, with lower switching supplying the remaining gain.
- PPA-Accuracy Trade-offs: 93% maximum AP reduction occurs under exhaustive stimulation, while the workload-based 56% result is more deployment-relevant.Changing CFG@[00] to CFG@ lowers AP by 10-17% under the real workload.
- Constraint Satisfaction: Every selected design satisfies all four WCE constraints across repeated runs.Some modes retain slack because WCE is a feasibility constraint, while all modes compete for the same logic.
- Area Variation: Seven of nine selected variants are smaller than the exact baseline.M1,1 and M2,1 remain slightly larger because CFG@[00] is bit-exact while multi-mode control remains present.
- RVS Ablation: At 16 bits, SAT-only passes nothing at 0.5 s while RVS still progresses.RVS moves unresolved candidates off the critical path, and its advantage disappears when the SAT limit is long enough to resolve candidates in-loop.
- RVS Ablation: 81-87% of verified passes come from fewer than 1% of fallback calls at 0.05-0.2 s.Fallback pass rate rises from 26% to 95% as the SAT limit increases, then fallback stops firing at 0.5 s.
- Adaptive-Mutation Ablation: 1.33× faster convergence: EWA α=0.05 reaches the 50% area target than fixed mutation.A larger α=0.20 gives the largest near-final 90% speedup of 1.32×.
4.2 Neural-Network Evaluation
The neural-network evaluation measures energy and accuracy when configurable multiplier modes replace exact multipliers in DNN inference. Results show energy savings and workload-dependent accuracy tolerance across CNNs and DeiTs.
- A shared 2-bit register enables offline per-layer mode selection without changing the systolic-array datapath.
- 10–21% energy savings are achieved by approximate modes, which consume 6.8 × 10−2 to 7.7 × 10−2 pJ per multiplication versus 8.56 × 10−2 pJ for the exact unit.
- LeNet-5 and ResNet-20 tolerate 5.5% WCE with accuracy losses of 0.10 and 1.48 percentage points relative to FP32.
- ResNet-18 tolerates 1% WCE with a 1.09-point loss, while ResNet-50 incurs a 1.36-point loss at 0.1% WCE.
- DeiT-Tiny and DeiT-Small lose 1.9–2.0 points at 1% WCE, indicating applicability beyond CNNs but a preference for tighter modes.
4.3 Bit-Width Scalability
CircuitsDNA scales to 12- and 16-bit multipliers and exhibits the same qualitative area-power trend: relaxing the WCE budget exposes lower-AP circuits.
- The 12- and 16-bit experiments use 20 and 3 seeds, respectively, with population size 2 and only the highest-accuracy mode.
- Relaxing the WCE budget exposes lower-AP circuits across the evaluated multiplier widths.
- Search completes in approximately 2 hours at 12 bits and 5 hours at 16 bits despite harder verification.
- The 16-bit experiment demonstrates feasibility beyond INT8 rather than providing a statistically matched cross-width PPA comparison.
4.4 Comparison with Existing Work
The comparison positions CircuitsDNA against automated fixed-accuracy methods and runtime-configurable designs that commonly depend on predefined approximation structures.
- Existing automated methods generally generate separate fixed-accuracy circuits, whereas runtime-configurable designs often rely on predefined approximation structures.
- Because prior works use different technologies, workloads, and error metrics, the comparison emphasizes capability coverage rather than numerical PPA results.
5 Conclusion
CircuitsDNA generates unified arithmetic circuits with runtime-selectable accuracy modes under independent mode-wise WCE constraints. The reported results combine efficiency gains, bounded neural-network accuracy loss, stall-free search, and faster convergence.
- Up to 56% area-power-product reduction is reported on the ResNet-20 INT8 workload, and 93% under exhaustive activity, relative to an exact multiplier.
- Across evaluated CNNs and DeiTs, accuracy loss relative to FP32 remains below 2% after fine-tuning under WCE budgets of ≤1%.
- RVS eliminates search stalls observed with synchronous verification across 8-, 12-, and 16-bit multipliers.
- Adaptive mutation accelerates convergence by up to 1.33× without relying on predefined approximation structures.