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Multi-Agent AI Design of a Nanowatt Biomedical Low-Pass Filter from Topology to Layout

Danial Noori Zadeh, Devanshu Prasad, Mohamed B. Elamien

arXiv:2610.28677v1cs.AR

TL;DR

Analog design lacks an end-to-end flow that accounts for layout parasitics and process variation. This paper uses a multi-agent framework to design a subthreshold biopotential low-pass filter from specification to layout. The resulting layout is DRC- and LVS-clean and meets the specification in nominal post-layout simulation, with lower input-referred noise than the reference at about equal power.

  • Problem

    Analog designs that meet specifications at schematic level can fail after layout extraction or across process corners because parasitics and process variation affect performance.

    Source: §I · p. 1

  • Method

    A researcher agent directs schematic and layout agents using memory, deterministic simulation and verification tools, and human approvals of the specification and layout plan.

    Source: §I · p. 1, B. Memory · p. 2

  • Results

    41.6% lower input-referred noise than the super-source-follower reference design at about equal power was achieved in post-layout simulation.

    Source: §I · p. 2

  • Takeaways & Limitations

    The agents delivered a DRC- and LVS-clean layout that meets the filter specification at nominal conditions despite subthreshold noise–power trade-offs and threshold-voltage sensitivity.

    Source: §V · p. 4

    The reported post-PEX cutoff range of 246.00–251.52 Hz comes from varying MOS process, supply, or temperature one at a time.

    Source: B. Comparison and Limitations · p. 4

Abstract

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We demonstrate a multi-agent framework that takes an analog circuit from topology synthesis to layout. A researcher agent directs schematic and layout agents, a four-tier memory stores the specification and lessons, and separate agents review the designs. Deterministic tools provide pass/fail simulation reports, symbolic analysis, graph-based netlist equivalence, parasitic injection, and extraction with DRC and LVS in every optimization trial. A human approves the specification and the layout plan. For a fourth-order, 250-Hz subthreshold biopotential low-pass filter, the researcher agent synthesized, through simulation-guided trial and error, a novel current-reuse architecture that shares a single dc bias branch between a super-source-follower biquad and a flipped-voltage-follower biquad. The agents completed a DRC- and LVS-clean layout in 130-nm IHP SG13G2 CMOS that meets the specification in nominal post-layout simulation, despite the noise-power trade-off and threshold-voltage sensitivity of subthreshold operation. The filter's input-referred noise over 0.5-200 Hz is 41.6% below that of the super-source-follower reference design at about equal core power.

I. INTRODUCTION

Analog design lacks a comparable end-to-end flow because layout parasitics and process variation can undermine schematic-level performance. This work applies a multi-agent design process to a nanowatt biopotential filter, from topology synthesis through layout.

I. INTRODUCTION

  • Analog design lacks an end-to-end flow comparable to digital design because layout parasitics and process variation can make a specification-compliant schematic fail after extraction or across process corners.Source: §I · p. 1
  • The test case requires a fourth-order, 245–255-Hz cutoff biopotential filter while balancing low power, small capacitors, and input-referred noise.At fixed cutoff in weak inversion, lower current forces smaller capacitors and increases kT/C noise.Source: §I · p. 1
  • A human set the specification and reference design and approved the layout plan; agents performed the other design and verification steps.Source: §I · p. 1
  • The framework combines a researcher agent, schematic-sizing and layout loops, four-tier memory, agent reviewers, and simulation, symbolic-analysis, and layout tools.Source: §I · p. 1
  • 41.6% lower input-referred noise than the super-source-follower reference design at about equal power was achieved in a DRC- and LVS-clean layout.The fourth-order, 250-Hz filter drew 11.91 nW and had 29.19 µVrms IRN over 0.5–200 Hz in post-layout simulation.Source: §I · pp. 1–2

II. BACKGROUND

The paper situates its filter design within agentic analog-design work and the coupled noise, power, area, and robustness constraints of subthreshold biopotential filters.

II. BACKGROUND

  • Prior agents address analog sizing, topology generation, memory reuse, and layout assistance, but the cited examples include designer-instructed layout and block-level design tasks.Source: §II · p. 2
  • At fixed cutoff in weak inversion, lower current reduces capacitor size and raises kT/C noise, while cutoff depends exponentially on threshold voltage.Source: §II · p. 2
  • Current reuse and follower-based biquads address subthreshold-filter trade-offs, but stacking biquads shares limited voltage headroom and high-impedance nodes remain sensitive to parasitics.Source: §II · p. 2

III. AGENTIC DESIGN FRAMEWORK

The framework assigns schematic and layout work to specialized agents under a researcher agent, with task-specific tools and review roles.

III. AGENTIC DESIGN FRAMEWORK

  • The researcher agent holds the specification and dispatches tasks to schematic and layout agents, which operate in separate contexts and return short reports.Source: A. Agent Hierarchy · p. 2
  • Five schematic agents analyze papers as testable hypotheses, simulate candidate netlists, verify sign-off, build schematics, and audit records.Source: A. Agent Hierarchy · p. 2
  • Layout agents start from the signed-off netlist; a parasitic-budget agent sets per-net budgets, while a designer builds a parameterized generator for reviewer checks.Source: A. Agent Hierarchy · p. 2

B. Memory

The framework combines retrieved, evidence-linked memory with deterministic simulation and layout tools, including symbolic analysis and verification.

B. Memory

  • Four CoALA memory types organize retrieved context, simulation logs, evidence-linked lessons, and procedural code and checks within agent context limits.Working context is capped at 20 kB, and lessons are superseded rather than deleted when later shown wrong.Source: B. Memory · p. 2

C. Agent-Friendly Tools

  • Simulation returns pass/fail results for each specification, while parasitic injection tests added capacitance, resistance, threshold offset, or leakage on the signed-off netlist.A corrected phase-lag measurement disqualified a candidate, and per-net budgets informed a route change to less-capacitive Metal5.Source: C. Agent-Friendly Tools · p. 2
  • The parameterized layout generator and optimizer verify layouts with DRC, LVS, extraction, and symmetry checks, while graph equivalence checks netlist connectivity and device models.LVS caught shorted nets in two of 66 limit-parameter builds and a generator error that dropped capacitor-array plates.Source: C. Agent-Friendly Tools · p. 2
  • Symbolic analysis derives transfer functions, pole-zero maps, and per-device noise transimpedances, matching pre-layout simulation within 0.03 dB up to 1 kHz.It also identified a pole pair turning real in 7 of 45 pre-layout PVT corners, which one-factor-at-a-time sweeps miss.Source: C. Agent-Friendly Tools · pp. 2–3

D. Independent Review and Human Approval

Separate designer and verifier agents independently check sign-off cells and rebuilt layouts, while the layout designer pauses for human approval of its plan.

D. Independent Review and Human Approval

  • The sign-off verifier re-netlists and re-simulates submitted cells, while the layout reviewer rebuilds GDS and reruns DRC, LVS, and extraction against parasitic budgets.Neither reviewer may fix a design, and the layout reviewer will not review a generator it wrote.Source: D. Independent Review and Human Approval · p. 3
  • The layout designer stops for human approval of its plan; one of the human’s four decisions accepted a phase miss at one corner.Source: D. Independent Review and Human Approval · p. 3

E. Feedback Loops and Decisions

Simulation-guided trials selected topology changes, while corner and mismatch failures prompted distinct design adjustments.

E. Feedback Loops and Decisions

  • Merging biquad B’s bias source and feedback device cut core power by 66% and drawn capacitance by 58% versus the unmerged stacked candidate, at the cost of 1.31 µVrms more IRN.The agents retained the merged device because it removed a bias-only noise source; a rail-tied bridge gate left the bridge in triode at −2.17 dB dc gain, so they used the bias reference.Source: E. Feedback Loops and Decisions · p. 3
  • At equal capacitance, branch stacking with a merged device cut core power by 67.5% and IRN by 18.1% versus the unstacked reference, while a floating differential capacitor cut drawn capacitance by 45.1% at equal response.The floating-capacitor test and dummy-row cost measurement followed the human’s area goal.Source: E. Feedback Loops and Decisions · p. 3
  • The stacked design passed only 1 of 22 process, supply, and temperature corners, prompting a shared three-device replica bias that reduced the max/min fc ratio from 3–38× to 1.01–1.02×.Source: E. Feedback Loops and Decisions · p. 3
  • On an unstacked candidate, enlarging all devices cost 21° of phase and failed the 330° phase-lag specification, so the agents enlarged only bias devices to raise Monte Carlo yield while retaining phase lag above 330°.Source: E. Feedback Loops and Decisions · p. 3

A. Filter and Post-Layout Performance

The fourth-order filter reuses bias across two distinct biquads, with nominal post-layout results and mismatch behavior evaluated after parasitic extraction.

A. Filter and Post-Layout Performance

  • A p-type common-gate bridge passes biquad B’s bias current into biquad A’s output, letting one 2.65-nA branch per half bias both biquads; all 15 devices operate in weak inversion.Biquad A resembles a super-source follower and B a flipped voltage follower; both input followers are p-type because SG13G2 lacks isolated NMOS.Source: A. Filter and Post-Layout Performance · p. 3, Figure 2 · p. 3
  • The shared replica uses 33% of the 7.942-nA core current but holds fc across MOS process corners; under mismatch, post-PEX fc is 248.62 ± 3.67 Hz over 1024 draws.The shared-current coupling shifts the isolated biquad Q values toward the Butterworth values.Source: A. Filter and Post-Layout Performance · pp. 3–4
  • The IHP SG13G2 layout occupies 0.228 mm2, with 53.6% in MIM capacitors, and is DRC- and LVS-clean.Source: Figure 4 · p. 4
  • Post-PEX extraction moved fc from 249.77 to 248.66 Hz while power and 0.5–200 Hz IRN of 29.19 µVrms remained within 0.02%.The post-PEX simulation is at tt, 27 °C, and 1.5 V.Source: Figure 3 · p. 3, A. Filter and Post-Layout Performance · p. 4
  • Across 1024 post-PEX draws, 50-Hz CMRR and PSRR averaged 52.2 and 53.4 dB, with worst values of 35.6 and 36.6 dB, respectively.Figure 5 reports mean and min–max for CMRR and PSRR, and fc, with specification limits dashed.Source: A. Filter and Post-Layout Performance · p. 4, Figure 5 · p. 4

B. Comparison and Limitations

The filter has the lowest reported FoM among the compared designs, while post-PEX cutoff frequency remains within 246.00–251.52 Hz under one-at-a-time variations; 16 of 45 full combinations meet every specification.

B. Comparison and Limitations

  • 6.4 fJ on core power and 7.4 fJ with the bias branches are the filter’s lowest FoM values, versus 8.3 fJ for.FoM is energy per pole per unit of dynamic range, so lower is better; Vi and IIP3, and thus DR and FoM, are evaluated at 0.2fc.Source: B. Comparison and Limitations · p. 4
  • 246.00–251.52 Hz is the post-PEX cutoff-frequency range under one-at-a-time MOS-process, supply, or temperature variation; 16 of 45 full combinations meet every specification.The supply range is 1.40–1.65 V and temperature range is 0–70 ◦C.Source: B. Comparison and Limitations · p. 4
  • Post-PEX THD at 50 mVpp rises with input frequency because the filter slew-limits near fc.The figure of merit is evaluated at 0.2fc, the low end of the 0.2–0.8fc range in Table I.Source: B. Comparison and Limitations · p. 4
  • ADO-LLM improves Bayesian-optimization sizing efficiency with LLM-proposed design points, but its fixed-topology sizing could not find the A/B gains that required topology changes.Source: B. Comparison and Limitations · p. 4

V. CONCLUSION

The paper presents a multi-agent framework that directs schematic and layout agents, demonstrating simulation-guided topology synthesis from specification to layout. The resulting clean layout meets specification at nominal conditions, with human approvals and future silicon measurement and symbolic-analysis work noted.

V. CONCLUSION

  • The agents delivered a DRC- and LVS-clean layout that meets specification at nominal conditions despite subthreshold noise–power trade-offs and threshold-voltage sensitivity.Source: §V · p. 4
  • A researcher agent directed schematic and layout agents, autonomously synthesizing a new topology through trial and error with simulator feedback between human approvals.Humans approved the specification and layout plan; deterministic tools, memory, and review guided the agents.Source: §V · p. 4
  • Future work will add symbolic circuit analysis to the agents’ simulator loop and measure the filter in silicon.The analysis is intended to test whether agents can discover new techniques rather than only combine and size known ones.Source: §V · p. 4

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