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GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han

arXiv:2005.00406v1eess.SPcs.LG

TL;DR

Analog transistor sizing is difficult because large design spaces, nonlinear trade-offs, and costly simulations make manual redesign demanding, while knowledge transfer across circuits remains limited. GCN-RL Circuit Designer combines reinforcement learning with graph convolutional processing of circuit topology to transfer sizing knowledge across technology nodes and topologies. The method reports higher FoMs than methods without transfer and stronger performance than conventional optimization, random search, and human designs.

  • Problem

    Analog transistor sizing is challenging and prior work has limited transfer of sizing knowledge between circuits, technology nodes, and topologies.

  • Method

    GCN-RL Circuit Designer uses reinforcement learning with a graph convolutional network that processes circuit topology graphs during transistor-sizing optimization.

  • Results

    GCN-RL consistently achieves the highest FoMs across four circuits and achieves much higher FoMs with transfer learning than methods without knowledge transfer.

  • Takeaways & Limitations

    The method supports more effective and efficient transistor sizing and design porting across technology nodes and circuit topologies.

Abstract

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Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance trade-offs, and fast technological advancements. Although there has been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black-box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search, and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.

I. INTRODUCTION

GCN-RL Circuit Designer addresses the labor-intensive, simulation-heavy nature of analog transistor sizing by transferring learned knowledge across technology nodes and circuit topologies. It combines reinforcement learning with topology-graph information processed by a graph convolutional network.

  • Motivation: Analog transistor sizing is labor intensive and time consuming because of large design spaces, slow simulations, and sophisticated performance trade-offs.Manual design requires topology analysis, equations, initial sizing, and extensive simulation-based fine-tuning.
  • Research gap: Limited prior research transferred transistor-sizing knowledge between different circuit topologies or technology nodes.Existing research largely targeted sizing for a single circuit.
  • Approach: GCN-RL trains an RL agent on one circuit and applies it to new circuits or the same circuit at new technology nodes.The goal is to reduce simulation cost without designing from scratch.
  • Approach: The method opens the black-box optimization loop by leveraging circuit topology graphs and using a GCN to process component connection relationships.The proposed representation embeds circuit domain knowledge into optimization.
  • Results: Experiments demonstrate knowledge transfer between different technology nodes and topologies, with GCN necessary for transfer between topologies.The paper identifies topology-aware feature extraction as important for cross-topology transfer.
  • Results: GCN-RL consistently achieves better performance than human experts, random search, ES, BO, and MACE.The paper presents this as a contribution of reinforcement learning as an optimization algorithm.

II. RELATED WORK

Prior transistor-sizing methods include knowledge-based planning, model-based optimization, simulation-based black-box optimization, and reinforcement learning. GCN-RL differs by incorporating circuit topology information and supporting knowledge transfer across circuits.

  • Transistor sizing: Knowledge-based methods use expert-defined plans and equations, but general plans are time consuming to derive and require continual maintenance for new technology.TAGUS is given as an example of this category.
  • Transistor sizing: Model-based methods optimize circuit-performance models, but building accurate models requires numerous simulations.Their advantage is described as obtaining global optima easily.
  • Transistor sizing: Simulation-based methods evaluate circuit performance with simulators such as SPICE and optimize the resulting black-box problem using BO, MACE, or ES.These methods differ from GCN-RL in their treatment of circuit structure.
  • Limitations of prior methods: BO and MACE have difficulty transferring knowledge between circuits because their output spaces are fixed, while ES retains good samples without summarizing design knowledge.Neither MACE nor ES leverages topology-graph information.
  • Deep reinforcement learning: Deep reinforcement learning has demonstrated transferability across task domains, motivating its use for automated and transferable transistor sizing.The paper contrasts this with supervised learning in its related-work discussion.
  • Graph neural networks: Graph neural networks process graph data; this work uses GCN to leverage topology information for analog transistor-sizing optimization.The paper distinguishes this use from prior GNN work that replaces an electromagnetic simulator.

III. METHODOLOGY

The paper formulates fixed-topology transistor sizing as a bound-constrained optimization problem, using a weighted FoM that combines normalized performance metrics and specification satisfaction.

  • Transistor sizing optimizes a parameter vector x over a bounded design space D_n for a fixed analog-circuit topology.
  • The Figure of Merit is the objective, defined as a weighted sum of normalized circuit-performance metrics.
  • When a required specification is unmet, the method assigns a negative FoM value.
  • The normalization uses predefined factors mmin_i, while wi adjusts the importance of the ith performance metric.
  • Performance aspects with upper bounds use mbound_i, preventing further improvement from increasing the objective after their requirements are satisfied.

B. Framework Overview

The framework represents a circuit as a graph, uses an RL agent to generate component actions, refines those actions under technology constraints, simulates the circuit, and feeds the FoM back for policy updates.

  • Each iteration embeds circuit topology as a graph whose vertices are components and edges are wires, then supplies transistor state vectors to the RL agent.
  • The actor processes graph components and generates an action vector for each node, with action formats varying across transistors, resistors, and capacitors.
  • The environment denormalizes actions from [-1, 1], enforces matching, precision, and technology-node bounds, then simulates the resulting circuit.
  • The RL state for each component combines its index, component type, and selected model features.
  • Continuous actions are used because discrete sizing spaces are too large and would lose relative-order information before parameter rounding.The action vector includes W, L, and M for NMOS and PMOS transistors.
  • The reward is the FoM, normally using equally weighted metrics, while alternative metric weights can also be accommodated.

D. Enhancing RL Agent with Graph Convolutional Neural Network

GCN-RL augments an actor-critic agent with graph convolutions that aggregate topology information, while DDPG trains continuous component actions through simulated rewards.

  • Graph Convolutional Neural Network: GCN layers aggregate neighboring transistor features, and seven stacked layers provide a global receptive field over the topology graph.
  • Graph Convolutional Neural Network: The GCN uses the adjacency matrix plus identity, degree normalization, trainable layer weights, and an activation function to transform node states.
  • RL Agent Architecture: The actor and critic use different component-aware encoders or decoders because circuit components have different action parameters.
  • RL Agent Architecture: The actor outputs pre-refined component parameters in [-1, 1], which are denormalized and refined into final parameters.
  • Training: DDPG trains the off-policy actor-critic agent for continuous control using replayed transitions, critic updates, and sampled policy gradients.
  • Ablation: The study compares GCN-RL with non-GCN RL, which removes neighborhood aggregation and therefore does not use topology information.
  • Transfer: The proposed agent transfers design knowledge by inheriting pretrained actor-critic weights, unlike BO and ES according to the framework comparison.

E. Knowledge Transfer

GCN-RL transfers sizing knowledge across technology nodes and, when design principles are shared, across circuit topologies by combining RL transfer with topology-feature extraction.

  • Transfer between Technology Nodes: A trained agent can be applied directly to the same circuit at different technology nodes because similar design principles persist across technologies.
  • Transfer between Technology Nodes: The transferred agent can retain learned relationships such as tuning input-pair transistors to change amplifier gain across technology nodes.
  • Transfer between Topologies: GCN enables transfer between topologies that share design principles by extracting features from their circuit graphs.

A. Comparison between GCN-RL and others

Across four real-world circuit baselines, GCN-RL achieves the highest FoM while balancing multiple performance metrics and supporting different design focuses.

  • A. Comparison between GCN-RL and others: GCN-RL achieves the highest FoM values across four circuit baselines compared with other algorithms.The comparison includes human expert design, random search, NG-RL, ES, BO, and MACE.
  • A. Comparison between GCN-RL and others: GCN-RL converges faster than NG-RL because GCN extracts topology features more effectively than a fully connected network.The paper compares GCN with pure FC analogously to CNN versus pure FC for image features.
  • A. Comparison between GCN-RL and others: For Two-TIA, GCN-RL satisfies all specifications, forms a balanced five-metric design, and achieves the highest FoM and GBW.The metrics are bandwidth, gain, power, noise, and peaking.
  • A. Comparison between GCN-RL and others: GCN-RL supports metric-specific design emphasis by assigning one metric a 10× larger weight than the others.The five focused experiments weight BW, gain, power, noise, or peaking more heavily; all but GCN-RL-4 achieve the targeted outcome described in the passage.
  • A. Comparison between GCN-RL and others: For Three-TIA and LDO, GCN-RL achieves low power and strong bandwidth for Three-TIA, and favorable settling-time, regulation, and PSRR results for LDO.Three-TIA uses bandwidth, gain, and power; LDO uses settling times, load regulation, PSRR, and power.

B. Knowledge Transfer Between Technology Nodes

The RL agent transfers designs from 180nm to larger and smaller technology nodes, producing better FoMs than no-transfer methods after the same limited training steps.

  • B. Knowledge Transfer Between Technology Nodes: The experiments transfer agents trained on 180nm to 250nm, 130nm, 65nm, and 45nm technology nodes.This tests transfer to both a larger node and smaller nodes.
  • B. Knowledge Transfer Between Technology Nodes: After 300 total steps, transfer learning produces much better Two-TIA results than training without transfer.The 300 steps comprise 100 warm-up steps and 200 exploration steps.
  • B. Knowledge Transfer Between Technology Nodes: After equal training steps on Three-TIA, transfer learning results are consistently better than results without transfer.The methods use identical random seeds during the warm-up stage, and Figure 7 shows rapid post-warm-up improvement with transfer.

C. Knowledge Transfer Between Topologies

GCN-RL transfers knowledge between related Two-TIA and Three-TIA topologies, outperforming NG-RL transfer and no-transfer GCN-RL under limited retraining.

  • C. Knowledge Transfer Between Topologies: After training on one transimpedance amplifier topology, agents are applied to the other for only 300 additional steps.The study evaluates both Two-TIA-to-Three-TIA and Three-TIA-to-Two-TIA transfer.
  • C. Knowledge Transfer Between Topologies: GCN-RL transfer consistently achieves higher FoMs than NG-RL transfer.NG-RL transfer has FoM barely at the same level as no transfer, indicating the graph features are important for transfer performance.

V. CONCLUSION

GCN-RL Circuit Designer combines GCN and RL for transferable transistor sizing across technology nodes and circuit topologies.

  • V. CONCLUSION: GCN-RL Circuit Designer uses GCN to incorporate topology information into an RL-based automatic transistor sizing method.The method transfers knowledge between technology nodes and different topologies.
  • V. CONCLUSION: Extensive experiments demonstrate better FoM and knowledge-transfer ability, supporting more effective and efficient transistor sizing and design porting.The conclusion states that transferability applies across technology nodes and even different topologies.
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