PaperlayerView exact revision on arXiv

Source-linked AI summary

Logical multi-qubit entanglement with dual-rail superconducting qubits

Wenhui Huang, Xuandong Sun, Jiawei Zhang, Zechen Guo, Peisheng Huang, Yongqi Liang, Yiting Liu, Daxiong Sun, Zilin Wang, Yuzhe Xiong, Xiaohan Yang, Jiajian Zhang, Libo Zhang, Ji Chu, Weijie Guo, Ji Jiang, Song Liu, Jingjing Niu, Jiawei Qiu, Ziyu Tao, Yuxuan Zhou, Xiayu Linpeng, Youpeng Zhong, Dapeng Yu

arXiv:2504.12099v1quant-ph

TL;DR

Quantum error correction still faces resource overhead, and multi-qubit logical entanglement in dual-rail superconducting qubits had remained unrealized. This work uses tunably coupled dual-rail transmons with erasure-biased protection to generate logical entangled states and a logical CNOT. The processor demonstrates a 98.8% fidelity logical Bell state, a three-qubit GHZ state with 93.9% fidelity, and a logical CNOT with 96.2% gate fidelity.

  • Problem

    Multi-qubit logical entanglement in dual-rail qubits remained unrealized, despite its importance for QEC and scalable quantum algorithms.

    Source: §I · p. 2

  • Method

    The work integrates tunably coupled dual-rail transmon qubits and uses static pair coupling for detectable T1 errors and reduced dephasing, with tunable couplers for logical entanglement.

    Source: §I · p. 2, §III · p. 4

  • Results

    The processor generates a logical Bell state with 98.8% fidelity, a three-qubit GHZ state with 93.9% fidelity, and a logical CNOT with 96.2% gate fidelity.

    Source: §VI · p. 6

  • Takeaways & Limitations

    The dual-rail system also offers promising applications in quantum networks and quantum metrology.

    Source: §VI · p. 6

    The logical CNOT fidelity is suboptimal; coupler architecture and entanglement pulse sequences remain targets for improvement.

    Source: §VI · p. 6

Abstract

from arXiv · show

Recent advances in quantum error correction (QEC) across hardware platforms have demonstrated operation near and beyond the fault-tolerance threshold, yet achieving exponential suppression of logical errors through code scaling remains a critical challenge. Erasure qubits, which enable hardware-level detection of dominant error types, offer a promising path toward resource-efficient QEC by exploiting error bias. Single erasure qubits with dual-rail encoding in superconducting cavities and transmons have demonstrated high coherence and low single-qubit gate errors with mid-circuit erasure detection, but the generation of multi-qubit entanglement--a fundamental requirement for quantum computation and error correction--has remained an outstanding milestone. Here, we demonstrate a superconducting processor integrating four dual-rail erasure qubits that achieves the logical multi-qubit entanglement with error-biased protection. Each dual-rail qubit, encoded in pairs of tunable transmons, preserves millisecond-scale coherence times and single-qubit gate errors at the level of $10^{-5}$. By engineering tunable couplings between logical qubits, we generate high-fidelity entangled states resilient to physical qubit noise, including logical Bell states (98.8% fidelity) and a three-logical-qubit Greenberger-Horne-Zeilinger (GHZ) state (93.5% fidelity). A universal gate set is realized through a calibrated logical controlled-NOT (CNOT) gate with 96.2% process fidelity, enabled by coupler-activated $XX$ interactions in the protected logical subspace. This work advances dual-rail architectures beyond single-qubit demonstrations, providing a blueprint for concatenated quantum error correction with erasure qubits.

I. INTRODUCTION

Quantum error correction can suppress logical errors exponentially, but practical implementation remains constrained by the resource overhead. The paper addresses the outstanding challenge of generating multi-qubit logical entanglement in dual-rail superconducting qubits, reporting entangled states and a logical CNOT gate.

I. INTRODUCTION

  • Exponential logical-error suppression through QEC requires redundant physical-qubit encoding, but practical schemes face quadratic resource overhead.Noise-biased qubits and detectable erasure channels are two strategies motivated by this challenge.Source: §I · p. 1
  • Dual-rail encoding assigns logical states to transmon pairs so physical T1 decay becomes detectable leakage, while strong coupling suppresses residual dephasing.Erasure-conversion QEC protocols have higher thresholds than conventional methods [5] [37].Source: §I · p. 1
  • Multi-qubit logical entanglement had remained unrealized, despite its importance for QEC and scalable quantum algorithms.The required challenges include tunable coupling between protected logical subspaces, converting operation errors into erasures, and erasure detection without compromising gate fidelity.Source: §I · pp. 1–2
  • The processor demonstrates logical Bell states at 98.8% fidelity, a three-qubit GHZ state at 93.5% fidelity, and a logical CNOT with 96.2% process fidelity.The CNOT fidelity is limited by coupler-induced decoherence.Source: §I · p. 2

II. DUAL-RAIL PROCESSOR

The processor combines dual-rail transmon pairs, ancillas for mid-circuit erasure detection, and tunable couplers for logical entangling operations. Although it contains four dual-rail qubits, a broken control channel leaves only the first three available.

II. DUAL-RAIL PROCESSOR

  • The processor contains four square-connected dual-rail qubits, but a broken Q4A control channel leaves only the first three available.Each logical qubit uses two capacitively coupled transmons and encodes its logical subspace in the pair's single-excitation manifold.Source: §II · p. 2
  • Each dual-rail qubit has a coupled ancilla for mid-circuit detection of leakage into |00⟩.The four ancilla resonators share a readout channel, enabling simultaneous mid-circuit measurement.Source: §II · pp. 2–3
  • Tunable couplers induce effective logical-subspace XX coupling, mediating a √iSWAP gate from which a logical CNOT can be synthesized.The coupler connects physical qubits QiA and QjB in neighboring dual-rail qubits.Source: §II · p. 3

III. ERASURE CHECK AND SINGLE QUBIT OPERATIONS

The section characterizes ancilla-based erasure checks and logical single-qubit operations. The logical qubit exhibits millisecond-scale relaxation, long CPMG coherence, and high single-qubit gate fidelity, with its transmon-pair coupling suppressing dephasing.

III. ERASURE CHECK AND SINGLE QUBIT OPERATIONS

  • Logical single-qubit rotations are driven by modulating either physical qubit after bringing the pair into resonance to establish its eigenstates.The logical-state energy gap is 150–180 MHz, depending on the qubit frequencies.Source: §III · p. 3
  • The two-photon ancilla-excitation check provides a larger dispersive shift and improved readout fidelity, so it is used in subsequent experiments unless noted otherwise.A conditional pulse excites the ancilla only when the dual-rail qubit is in |00⟩; logical-space states leave it in the ground state.Source: §III · pp. 3–4
  • The logical T1 is 0.98 ms, the CPMG T2 is 0.66 ms, and the average single π/2 gate fidelity is 99.9974%.Coherence times are approximately an order of magnitude longer than those of corresponding physical qubits; benchmarking postselects shots without erasure.Source: §III · p. 4
  • Strong transmon-pair coupling suppresses low-frequency frequency noise, producing a large erasure-noise bias and reducing logical-subspace dephasing.For coupling g much greater than frequency difference δ, the dual-rail energy gap is approximately 2g + δ^2/4g.Source: §III · p. 4

IV. TUNABLE COUPLING AND ROBUST ENTANGLEMENT

The tunable-coupler protocol generates a high-fidelity logical Bell state whose entanglement persists substantially longer than its physical-qubit counterpart. Coupler-induced decoherence remains a source of infidelity during the swap operation.

Tunable coupling

  • High-fidelity logical √iSWAP requires matched logical frequencies and physical-qubit detuning large relative to inter-qubit coupling and qubit nonlinearity.The physical coupling strength is tuned adiabatically to implement the gate.Source: §IV · p. 5
  • At the swap frequency, a second-order XX interaction exchanges logical |01⟩L and |10⟩L states, with leakage detectable as erasure errors.The coupler is tuned from an idle point with zero logical ZZ interaction to the swap frequency, where the logical states are resonant.Source: §IV · p. 5

Logical Bell-state generation and protection

  • 98.8(1)% Bell-state fidelity; logical entanglement persists roughly ten times longer, retaining 93.5(4)% at 20 µs and above 70% beyond 100 µs.The Bell-state fidelity is 98.8(1)% after generation; the longer storage time is compared with a physical-qubit Bell state.Source: §IV · pp. 5–6

Infidelity source

  • Coupler tuning to ωswap induces decoherence through strong qubit-coupler hybridization, reducing Bell-state fidelity despite millisecond-scale idle coherence.The authors attribute the additional decoherence to the coupler frequency approaching a physical-qubit frequency.Source: §IV · p. 6

V. LOGICAL MULTI-QUBIT ENTANGLEMENT

A logical CNOT assembled from iSWAP and single-qubit gates achieves 96.2(3)% process fidelity and supports preparation of a three-qubit logical GHZ state with 93.9(2)% fidelity. Coupler-induced decoherence is identified as a source of infidelity in both operations.

CNOT synthesis

  • A logical π pulse between two iSWAP gates mitigates accumulated ZZ phase, while single-qubit gates compensate phases from coupler tuning.The resulting logical CNOT is described as ZZ-free.Source: §V · p. 6

Logical multi-qubit entanglement

  • 96.2(3)% CNOT process fidelity and 93.9(2)% three-qubit GHZ state fidelity demonstrate logical multi-qubit entanglement.The GHZ state is reconstructed by quantum state tomography in the logical subspace.Source: §V · p. 6

GHZ-state preparation

  • The GHZ sequence initializes three dual-rail qubits and applies a logical CNOT between the second and third qubits after preparing the first pair.The prepared state is (|000⟩L + |111⟩L)/√2.Source: §V · p. 6, Figure 4a

Infidelity source and scope

  • Additional decoherence induced by the coupler at ωswap could account for infidelity in both the CNOT gate and GHZ state.The authors also note that their protocol can generate logical iSWAP gates for surface-code circuits without additional overhead [60].Source: §V · p. 6

VI. DISCUSSION AND OUTLOOK

The work reports logical entanglement using tunably coupled dual-rail qubits, including a Bell state, a CNOT gate, and a three-qubit GHZ state. The authors identify suboptimal CNOT fidelity and coupler and pulse refinements as areas for improvement.

Results

  • 98.8% Bell-state fidelity, 96.2% CNOT fidelity, and 93.9% three-qubit GHZ fidelity summarize the demonstrated logical entanglement results.The Bell-state entanglement storage time is reported as an order of magnitude longer than that of its physical counterpart.Source: §VI · p. 6

Outlook

  • The authors describe the current logical CNOT fidelity as suboptimal and target coupler architectures and entanglement pulse sequences for improvement.They note that millisecond-scale dual-rail coherence suggests coherence-limited fidelity could exceed 99.9%.Source: §VI · p. 6

Related work

  • A relevant experiment reported during manuscript preparation also demonstrated a two-qubit entangling gate for dual-rail erasure qubits, using 3D superconducting cavities [67].Source: §VI · p. 6

Competing interests

The paper declares no competing interests, makes supporting data available from the corresponding authors upon request, and identifies supplementary information for the study.

Competing interests

Data availability

  • Data supporting the plots and other findings are available from the corresponding authors upon request.Source: Data availability · p. 7

Supplementary Information for “Logical multi-qubit

I. EXPERIMENTAL SETUP AND DEVICE INFORMATION

The setup combines a multiplexed processor and low-temperature control wiring with a multi-stage readout chain.

I. EXPERIMENTAL SETUP AND DEVICE INFORMATION

  • The processor has eight data qubits, four ancillas, four tunable couplers, and three readout lines, with four qubits interrogated per line.It is thermally anchored at 10 mK.Source: §I · p. 10
  • Low-temperature bias-tee combination of slow-bias and fast signals reduces thermal noise and enhances coherence in the dual-rail logical space.The control system uses 2 Gs/s DACs and 1 Gs/s ADCs.Source: §I · p. 10

The readout chain features a multi-stage amplification scheme. At the preamplifier stage,

  • Ancilla readout uses an IMPA preamplifier, a HEMT amplifier at 4 K, and additional room-temperature amplification.Circulators and filters limit noise reaching the chip and backflow from the IMPA.Source: The readout chain features a… · p. 10

our flip-chip architecture, the pad-pad capacitance of floating qubit is substantially smaller

This section describes the processor’s signal routing and coupling design, then characterizes ancilla spectra and erasure-check readout performance.

our flip-chip architecture, the pad-pad capacitance of floating qubit is substantially smaller

The coupling geometries in qubit chip comprises two configurations: (1) the Data-Ancilla

continuous tunability via the coupler frequency ωC12

  • The dual-rail readout parameters include drive frequencies, relaxation and CPMG dephasing times, and joint-readout fidelities for logical and |00⟩ states.The supplied passage defines these quantities but gives no numerical values.Source: continuous tunability via the coupler… · p. 15

II. ANCILLA QUBIT SPECTRA

  • The ancilla’s spectral-peak detuning increases as its frequency approaches the data-qubit frequency, and a fitted Hamiltonian model estimates gAB = 85 MHz versus a measured 76 MHz.The model is used to select ancilla frequency for desired erasure-check spectral properties.Source: BaA) · p. 17, §II · p. 17

III. ERASURE CHECK FIDELITY

  • The IMPA provides approximately 20 dB gain across a 1 GHz range covering all four ancillas, while the ancilla-check I-Q clouds have SNR 3.8.The check uses the ancilla and a two-photon excitation scheme.Source: §III · p. 18
  • 97.4% was the measured average ancilla readout fidelity, below the 99.7% upper bound associated with 0.3% separation error.The measured I-Q signal-to-noise ratio was 3.8.Source: §III · pp. 18–19

by state preparation error and T1 relaxation during the readout pulse.

Ancilla checks identify erasures with low false-positive and false-negative rates, while repeated checks and CPMG sequences extend logical coherence. The section also describes single-qubit calibration and coupler tuning that produces a logical interaction and enables phase-corrected gates.

by state preparation error and T1 relaxation during the readout pulse.

  • 2.1% false negatives and approximately 0.5% false positives were measured for ancilla erasure checks after postselection removed T1 relaxation effects from the measurement.False negatives occur when an erased |00⟩ state is read as |0⟩; false positives occur when a logical state is read as |2⟩.Source: by state preparation error and T1… · pp. 19–20

T2 decay process. By repeatdly applying ancilla checks, the coherence can last much longer

enhancement of T1 is achieved in the dual-rail qubit compared to its physical counterpart.

V. CALIBRATION OF LOGICAL SINGLE QUBIT GATES

and DRAG parameters, and determining the optimal parameter set by minimizing P|0L⟩.

To verify the presence of a logical XX interaction at ωswap, we perform logical qubit

With coupler frequency near ωswap, coherent population exchange between |01⟩L and |10⟩L

  • The coupler-flux setting that maximizes logical population-exchange visibility determines the √iSWAP pulse parameters.The gate duration is identified where the |01⟩L and |10⟩L populations become equal.Source: With coupler frequency near ωswap,… · p. 25

logical CNOT gate by using two logical

For single-qubit gates, the coherence-limited gate error [3] is given by ε = τ/3T1 +τ/3Tϕ,

The section estimates single-qubit coherence-limited error and compares it with measured gate performance. It also reports elevated CNOT error and a coherence reduction at the interaction frequency, while bounding gate error under assumptions about decoherence during the pulse.

For single-qubit gates, the coherence-limited gate error [3] is given by ε = τ/3T1 +τ/3Tϕ,

  • 1.7 × 10−5 is the estimated coherence-limited single-qubit gate error, close to the measured value.The estimate uses τ = 25 ns, T1 = 980 µs, and Tϕ = 995 µs.Source: For single-qubit gates, the… · p. 30

The logical CNOT gate comprises two

by T1 relaxation and white noise dephasing Tϕ: ε = P

  • The first dual-rail qubit’s T1,L and T2,L fall from several hundred microseconds at idle to a few microseconds at the interaction frequency; error bounds assume plateau-only decoherence for the lower bound and uniform pulse decoherence for the upper bound.The effect is less pronounced for the second dual-rail qubit because its physical qubits operate at lower frequencies.Source: For single-qubit gates, the… · p. 30, by T1 relaxation and white noise… · p. 30

(τ = 150 ns). This approach yields an estimated error of 0.8%–2.5% for a single

The logical CNOT error estimate is 1.7%–5%, consistent with the observed 3.8% gate error. Coupler-induced decoherence is identified as the main contributor, with improved coupler designs and pulse sequences proposed for optimization.

iSWAP

  • A 1.7%–5% logical CNOT error estimate aligns reasonably with the observed 3.8% gate error.The estimate is reported as the result of the method described in this section.Source: iSWAP · p. 30
  • Coupler-induced decoherence is the predominant contributor to the substantial gate error.Maintaining dual-rail coherence at idling values could elevate gate fidelity beyond 99.9%.Source: iSWAP · p. 30
  • The comparison concerns logical coherence time of two coupled dual-rail qubits while the coupler is at ωidle and ωswap.The supplied table caption identifies the compared quantity; the supplied passage does not state a comparison outcome.Source: Table S5 · p. 31, iSWAP · p. 31
Loading 2504.12099v1…