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The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes
Paul Webster, Lucas Berent, Omprakash Chandra, Evan T. Hockings, Nouédyn Baspin, Felix Thomsen, Samuel C. Smith, Lawrence Z. Cohen
TL;DR
Utility-scale quantum computing needs fault-tolerant architectures with lower overhead than surface-code designs. The paper introduces the Pinnacle Architecture using QLDPC codes, bridged code blocks, modular surgery gadgets, a magic engine, and flexible parallelism. It reports 2048-bit RSA factoring with fewer than one hundred thousand physical qubits at p = 10^-3, with a 1 μs code cycle and 10 μs reaction time.
Problem
Surface-code fault-tolerant architectures require at least one million physical qubits for utility-scale computations, making lower-overhead architectures important.
Source: §I · p. 1Method
Results
Fewer than one hundred thousand physical qubits suffice for 2048-bit RSA factoring at p = 10^-3, with a 1 μs code cycle and 10 μs reaction time.
Source: B. Results · p. 2, §4 · p. 17Takeaways & Limitations
The architecture reduces the reported RSA-factoring qubit requirement by roughly an order of magnitude relative to the previous best result and supports a spacetime trade-off through parallelisation.
Source: B. Results · p. 2, §VII · p. 18
Abstract
from arXiv · showhide
The realisation of utility-scale quantum computing inextricably depends on the design of practical, low-overhead fault-tolerant architectures. We introduce the \textit{Pinnacle Architecture}, which uses quantum low-density parity check (QLDPC) codes to allow for universal, fault-tolerant quantum computation with a spacetime overhead significantly smaller than that of any competing architecture. With this architecture, we show that 2048-bit RSA integers can be factored with less than one hundred thousand physical qubits, given a physical error rate of $10^{-3}$, code cycle time of $1$ \textmu s and a reaction time of $10$ \textmu s. We thereby demonstrate the feasibility of utility-scale quantum computing with an order of magnitude fewer physical qubits than has previously been believed necessary.
I. INTRODUCTION
The Pinnacle Architecture uses QLDPC-based modular components and parallelism techniques to reduce fault-tolerant quantum-computing overhead. Resource estimates show order-of-magnitude reductions for Fermi–Hubbard simulation and RSA-2048 factoring across hardware regimes.
A. Pinnacle Architecture
- Processing units use bridged QLDPC blocks and measurement gadgets, while magic engines distill and inject one high-fidelity magic state per logical cycle for each processing unit.Optional memory provides low-overhead storage accessed through ports.Source: §I · p. 1, A. Pinnacle Architecture · p. 2
- The architecture is compiled through Pauli-based computation, supporting universal fault-tolerant computation on arbitrarily many logical qubits with cost scaling in T count.A concrete implementation uses generalised bicycle codes and modular measurement gadgets [11].Source: A. Pinnacle Architecture · p. 2, B. Results · p. 2
- QLDPC codes reduce physical-qubit overhead without the corresponding time increase of the bicycle architecture by enabling arbitrary logical Pauli measurements through efficient gadgets.The architecture therefore targets lower total spacetime overhead than prior fault-tolerant architectures.Source: §I · p. 1, A. Pinnacle Architecture · p. 2
- Clifford frame cleaning enables parallel operations across processing units and parallel read-only memory access, while connectivity remains limited to bounded-distance interactions.The modular design supports hardware with quasi-local connectivity rather than all-to-all connections.Source: §I · p. 1, A. Pinnacle Architecture · p. 2
B. Results
- 62,000 physical qubits at L = 16 and p = 10^-3, or 22,000 at p = 10^-4, achieve Fermi–Hubbard energy estimation, versus 940,000 and 200,000 with surface codes.The estimates maintain runtimes of 1–4 minutes per shot with microsecond cycles or 1–3 days with millisecond cycles.Source: B. Results · p. 2
III. BACKGROUND
The background defines QLDPC code blocks, processing blocks, logical operations, and the timescales used for resource estimates. Measurement gadgets extend QLDPC blocks to support arbitrary logical Pauli measurements and universal computation.
A. Code Blocks
- QLDPC codes have constant-bounded check weights and qubit degrees, allowing constant-depth syndrome extraction circuits that remain fault tolerant.A logical cycle combines Θ(d) code cycles to obtain a reliable syndrome.Source: A. Code Blocks · p. 5
B. Processing Blocks
- A processing block appends a generalised-lattice-surgery measurement gadget to a QLDPC code block, enabling logical Pauli measurements during syndrome extraction.Bridged gadget systems support arbitrary logical Pauli measurements across multiple processing blocks [24] [25] [26] [28] [29].Source: B. Processing Blocks · p. 5
- Injected magic states combined with bridged logical measurements enable universal computation through Pauli-based computation [13].A circuit with T count τ on κ qubits can use τ + κ Pauli measurements and one |T⟩ state for each of the first τ measurements [6].Source: C. Pauli-Based Computation · p. 5
D. Relevant Timescales
- The code cycle time t_c is one syndrome-extraction round, while the logical cycle time is t_l = d_t t_c because a logical cycle contains d_t code cycles.The code cycle time is hardware-dependent, with estimates ranging from 1 µs to 1 ms [16] [22] [30] [31] [32].Source: D. Relevant Timescales · p. 5
- Reaction time t_r is the minimum interval before an adaptively dependent measurement can begin; resource estimates assume t_r = 10t_c.This makes the architecture non-reaction-limited when d_t ≥ 10, which holds for the presented estimates.Source: D. Relevant Timescales · p. 5
IV. THE PINNACLE ARCHITECTURE
The Pinnacle Architecture combines QLDPC-based processing units, magic engines, optional memory, and Pauli-based computation into a modular fault-tolerant architecture. Its magic engines distill and deliver encoded magic states continuously, while memory ports support parallel read-only access.
Architecture modules
- The architecture comprises processing units, magic engines, and optional memory, with operation built incrementally from serial computation toward more general modes.Processing units perform logical Pauli measurements; magic engines supply states for universal computation; memory stores logical qubits accessed through ports.Source: §IV · p. 6, §1 · p. 6, §2 · p. 6
Processing units
- Each processing unit uses β QLDPC processing blocks to support κ := βk logical qubits and arbitrary logical Pauli measurements in each logical cycle.Nearest-neighbour bridges connect the processing blocks, allowing measurements supported on any subset of the unit’s logical qubits.Source: §1 · p. 6
Magic engines
- Each magic engine distills and consumes encoded |T̄⟩ states in alternating logical sectors, providing a state for the associated processing unit while preparing the next one.The two sectors swap roles in alternating cycles; injection uses joint logical measurements involving the processing unit and a logical operator on the consuming sector.Source: §2 · p. 6, Figure 4 · p. 6
- Post-selection rejects the produced state with probability p_r, increasing the expected logical cycles per T gate from 1 to α = (1 − p_r)^−1.If a required state is rejected, the processing unit can remain idle for the next logical cycle while a replacement is prepared.Source: §2 · p. 6
Memory
- Memory stores μ = νk_m logical qubits in ν QLDPC code blocks and can provide parallel read-only access through ports assigned to windows of w qubits.With suitable parallel port gadgets, up to νk_m/w processing units can access memory simultaneously; blocks are permuted using bounded shifts.Source: §3 · pp. 6–7
Serial operation
- In serial operation, a κ-qubit Clifford+T circuit with T count τ and o intermediate measurements takes an average of τ/(1 − p_r) + κ + o logical cycles.Each cycle consumes a magic state through a joint Pauli measurement while the magic engine prepares the state for the next cycle.Source: §1 · p. 7
2. Fully Parallel Operation
The architecture supports fully and flexibly parallel computation by distributing independent circuits across processing units and cleaning entangling Clifford frames when separation becomes advantageous. This avoids implementing every inter-unit CNOT physically while retaining opportunities for runtime savings.
Fully Parallel Operation
- Independent circuits can run on separate processing units in parallel, reducing logical timesteps to approximately the maximum per-circuit workload rather than the sum.The approximation omits a correction from differing magic-state rejection proportions, assumed negligible when T counts are large.Source: §2 · p. 7
- Parallel execution is useful for multiple algorithm shots because additional qubits can reduce runtime relative to performing all shots serially.This mode applies when a circuit separates completely into independent circuits.Source: §2 · p. 7
Flexibly Parallel Operation
- Entangling gates spread the Clifford frame across processing units, preventing simultaneous T-gate measurements because each unit permits only one logical measurement per cycle.A T-state injection measurement on one unit can therefore acquire support on both units after an inter-unit entangling operation.Source: §3 · pp. 7–8
- Physically implementing every inter-unit CNOT can erase parallelism benefits because its time cost scales with the number of entangling gates, especially when only some circuit regions are parallelisable.Parallelism requires the Clifford frame to factor as a tensor product across the units being parallelised.Source: §3 · p. 8
- Clifford frame cleaning physically applies a Clifford that acts trivially on a selected subset, using at most 4|K′| logical Pauli product measurements.This provides a lower-cost alternative to physically implementing every CNOT gate used to entangle processing units.Source: §3 · p. 8
- Units join after inter-unit entangling gates and can later separate through cleaning, allowing parallel-friendly circuit regions to run concurrently with potential time savings.The choice of when to separate can be optimised for the compiled circuit; the joining process can temporarily force measurements to be serial.Source: §3 · p. 8
4. General Operation
General operation adds read-only memory access and scalable modular hardware support to the architecture. A concrete generalised-bicycle-code instantiation supplies the code blocks, gadgets, bridges, and syndrome-extraction parameters used for evaluation.
4. General Operation
- Processing units access memory through ports by joining the relevant memory window during logical CNOT fanout, while distinct memory ports remain separable.This supports read-only access using controls on memory-port qubits and targets on ancillary processing-unit qubits.Source: §4 · p. 9
- The architecture supports arbitrarily large processing units with physical connectivity confined to a constant scale, approximately √n_pb in a two-dimensional layout.Nearest-neighbour bridges connect processing blocks, so logical operators spanning blocks need no long-distance routing.Source: C. Scalability · p. 9
- Logical-operation changes and routing remain confined to processing-block scale, supporting hardware whose interaction fidelity decreases continuously with distance.Code choice and gadget design can further reduce the required dynamism.Source: C. Scalability · p. 9
- The modular structure aligns processing units with smaller hardware modules, enabling architecture–hardware co-design subject to connectivity between modules that may be joined.Each processing unit must be adjacent to its magic engine and, when present, an associated memory port.Source: C. Scalability · p. 9, D. Structure · p. 9
Code instantiation
- The evaluated instantiation uses generalised bicycle codes, whose code blocks have n = 2l physical qubits divided into L and R sectors and support cyclic-shift automorphisms.The selected family has weight-six parity checks, short-distance syndrome-extraction transport, and conjectured parameters specified by m.Source: §V · p. 9, A. Setup · p. 10
- The implementation uses d_t = d + 2 code cycles per logical cycle, reflecting empirical improvement from performing slightly more syndrome-extraction rounds than the code distance.Processing blocks add four gadgets and four bridges per block, with physical-qubit totals determined by gadget, bridge, and check-qubit counts.Source: A. Setup · p. 10
- Duplicate gadgets can measure multiple logical operators in one logical cycle when the operators commute qubit-wise.The condition ensures that check operators from the different gadgets commute.Source: A. Setup · p. 10
B. Modules
The architecture combines processing blocks, magic engines, and modular memory using GB codes and generalized-surgery gadgets. These modules support logical measurements, magic-state preparation, parallel access, and resource-efficient encoding.
Processing blocks
- 14β logical qubits fit in 860β physical qubits at d = 16, while d = 24 encodes 16β logical qubits in 1620β physical qubits.These processing blocks use β blocks and encode κ = βk logical qubits.Source: §1 · p. 10
Magic engines
- The magic engine supplies one high-fidelity magic state per processing unit per logical cycle through injection, distillation, and post-selection.Its output fidelity can approach 35p_in^3 with rejection rate approximately 15p_in, subject to QLDPC and timing requirements.Source: §2 · pp. 10–11
- At p = 10^-4, the magic engine uses d_a = 5 ancilla codes, d_e = 10 GB blocks, and has n_me,10^-4 = 2128 physical qubits.The protocol assumes r ≥ 7 X-type measurement rounds and completes within one logical cycle for processing blocks with d ≥ 10.Source: §2 · p. 11
- At p = 10^-3 with d = 24 processing blocks, d_a = 9 rotated surface codes and r ≥ 13 measurement rounds provide the required magic-state throughput and logical-error protection.Two copies of a 25-physical-qubit ancilla system per surface code add n_α = 750 ancilla qubits.Source: §2 · pp. 11–12
Memory
- Memory stores 14ν or 16ν logical qubits with parallel access from ρ processing units using 508ν + 88ρ physical qubits at d = 16 or 1020ν + 150ρ at d = 24.Each memory port adds 88 physical qubits at d = 16 or 150 at d = 24.Source: §3 · p. 12
C. Simulation Results
The simulations estimate logical failure rates for memory and generalized-surgery measurements across GB code distances and physical error rates, guiding code-distance choices for resource estimation. The section also specifies the Fermi–Hubbard estimation procedure and its resource-counting assumptions.
Logical-error simulations
- Logical error rates are simulated for memory and generalized-surgery measurements over one logical cycle under circuit-level depolarizing noise.Memory simulations use d syndrome-extraction rounds and rescale failure rates by (d + 2)/d; one logical cycle contains d + 2 rounds.Source: C. Simulation Results · p. 12, Figure 6 · p. 12
- The fitted ansatz yields logical error rates per logical qubit and cycle for GB codes at physical error rates p = 10^-3 and p = 10^-4.Table III derives these rates from fitted parameters for each considered code distance.Source: C. Simulation Results · p. 12, Table III · p. 13
Decoder choice
- Most-likely error decoding is selected because it correctly decodes all faults of weight less than d/2 and avoids error floors associated with alternatives such as belief-propagation decoders.Developing a sufficiently fast real-time decoder is outside the paper’s scope.Source: C. Simulation Results · pp. 12–13
Fermi–Hubbard resource estimation
- The Fermi–Hubbard calculation uses plaquette Trotterisation with a target relative error of 0.5% while omitting Hamming-weight phasing to reduce the logical-qubit requirement.The simplification replaces ancillary-qubit-heavy phasing with sequential phase rotations.Source: §1 · p. 13
- For this algorithm, two logical qubits are allocated per lattice site plus two ancillas, while Trotter-step costs include T gates and synthesized arbitrary Z rotations.The number of Trotter steps is set by the target precision and a bound on Trotter error.Source: §1 · p. 13
2. Implementation and Results
The architecture is instantiated for Fermi–Hubbard energy estimation and evaluated for its physical-qubit and runtime requirements. It also frames the architecture as applicable to RSA factoring, while accounting for repeated shots and parallel resource trade-offs.
Fermi–Hubbard implementation and results
- For even L ≤ 32 at u = 4, the Fermi–Hubbard algorithm uses at most N ≤ 2050 logical qubits and T = 8 × 10^6 logical cycles.The resulting logical spacetime volume is bounded by NT ≤ 2 × 10^10, requiring pL ≪ 5 × 10^-11 and pT ≪ 10^-7 for negligible failure probability.Source: §2 · p. 14
- The implementation uses one processing unit with enough processing blocks to provide κ ≥ N logical qubits, together with a magic engine but no included memory.The physical-qubit count is obtained from the processing-block, magic-engine, and block-count parameters.Source: §2 · p. 14
- The required physical-qubit estimates are obtained by substituting N = 2L^2 + 2 and the resource parameters for physical error rates p = 10^-3 and p = 10^-4.These substitutions determine the architecture-specific resource estimates.Source: §2 · p. 14
- The physical-qubit requirement is an order of magnitude below surface-code estimates, with runtimes reported for 1 μs and 1 ms code-cycle times.Table IV covers even lattice sizes up to L = 32 and targets relative error no greater than 0.5% of total lattice energy.Source: §2 · p. 14, Table IV · p. 14
- Complete Fermi–Hubbard energy estimation requires multiple shots whose count depends on initial-state overlap, with parallel shots trading additional processing units for shorter runtime.Shots may instead be performed serially with proportional runtime increase.Source: §2 · p. 14
1. Algorithm
The algorithm generalises Gidney’s factoring method by processing residue-system primes in parallel, reducing runtime while reusing a shared input register. It is compiled onto Pinnacle processing units, memory, ports, and magic engines to account for physical resources and runtime.
Parallelised factoring algorithm
- Parallel processing of ρ residue-prime subsets reduces the algorithm’s time cost to approximately ⌈|P|/ρ⌉ times Gidney’s cost, plus O(log ρ) reduction overhead.For RSA-2048, |P| is approximately 2.1 × 10^4, allowing potentially many orders of magnitude in time reduction.Source: §1 · p. 15
- The parallelisation duplicates the Θ(log log N_RSA) working register but reuses the Θ(log N_RSA) input register, so space grows less than proportionally to the time reduction.Pipelined windowed accesses allow multiple working registers to share a single input register.Source: §1 · p. 15
- The modified algorithm achieves orders-of-magnitude lower time overhead with a smaller space increase and can outperform the earlier Gidney–Ekerå implementation.This motivates its use even when the architecture has slow clock cycles.Source: §1 · p. 15
Pinnacle implementation
- Each working register is assigned a processing unit, while independent modular-exponentiation streams run in parallel and are joined during the final accumulator reduction.The processing units are provisioned with κ logical qubits, where κ = f + 2ℓ + len(m) + 2 max(f, ℓ + len(m)) + 1.Source: §2 · pp. 15–16
Resource accounting
- The resource model includes shared or replicated input memory, ports, logical-cycle counts, T-state rejection, shot success probability, and total runtime per factoring attempt.Total physical qubits combine processing-unit and memory resources, while runtime is computed from logical cycles and the cycle duration.Source: §2 · p. 16, §3 · p. 16
4. Results
The results optimise algorithmic parameters and the parallelisation factor across hardware regimes to estimate RSA-2048 factoring resources. Under standard assumptions, Pinnacle requires fewer than one hundred thousand physical qubits, with explicit space–runtime trade-offs across error rates and cycle times.
RSA-2048 factoring
- Table VI reports the minimum physical-qubit count required to complete factoring across expected runtimes and hardware parameters.Mq denotes megaqubits and kq denotes kiloqubits.Source: Table VI · p. 17
- 151 thousand physical qubits enable one-week factoring, 471 thousand enable one-day factoring, and one million enable ten-hour factoring at p = 10^-3 and the same cycle parameters.The one-million-qubit runtime is five days in Ref. [8].Source: §4 · p. 17
Alternative hardware regimes
- At p = 10^-4, the minimum factoring requirement is 53 thousand physical qubits; with a 1 ms code cycle and one million qubits, the expected runtime is approximately three months.These parameters are described as relevant to trapped-ion platforms.Source: §4 · p. 17
- For neutral-atom parameters with p = 10^-3 and a 1 ms code cycle, 19 million qubits yield a 21-day runtime, compared with 5.6 days in Ref. [16].The comparison reflects a longer logical-cycle factor in the presented architecture, while Ref. [16] uses transversal gates with algorithmic fault tolerance.Source: §4 · p. 18
VII. CONCLUSION
The Pinnacle Architecture uses QLDPC codes to reduce fault-tolerant quantum-computing overhead and factors RSA-2048 with fewer than one hundred thousand physical qubits. The authors present this as both a major result and a foundation for further QLDPC-based reductions.
Conclusion
- QLDPC codes provide order-of-magnitude overhead reductions relative to surface-code architectures, enabling RSA-2048 factoring with fewer than one hundred thousand physical qubits instead of close to one million [8].The conclusion frames this reduction as addressing the hardware scale challenges of utility-scale quantum computing.Source: §VII · p. 18
Future prospects
- Higher-rate QLDPC codes and further component optimisation could plausibly reduce RSA-2048 resources further, making this architecture a foundation for continued progress.The codes used here are generalised bicycle codes, while a range of higher-rate QLDPC codes is known [18].Source: §VII · p. 18
Appendix A: Cost of Clifford Frame Cleaning
The appendix formalises Clifford frame cleaning using Pauli π/4 rotations represented through symplectic Pauli and Clifford algebra. It proves that operations affecting selected qubits can be transformed into support on the remaining qubits with bounded rotation counts.
Symplectic representation
- Pauli operators are encoded as vectors in Z_2n, with commutation determined by the symplectic inner product; Clifford operators act through symplectic matrices.A Pauli π/4 rotation adds its axis vector to an anticommuting Pauli and leaves commuting Paulis unchanged.Source: Appendix A · p. 18
General Clifford frame cleaning
- A general n-qubit Clifford operator can be cleaned from w selected qubits using 4w Pauli π/4 rotations, leaving a Clifford operator supported on the remaining n − w qubits.The proof proceeds inductively by mapping successive rows to standard symplectic-basis vectors while preserving previously fixed operators.Source: Appendix A · pp. 18–19
Proof strategy
- The induction constructs rotations that fix already-cleaned subspaces and progressively map selected rows to basis vectors, completing the support reduction.The same strategy is applied to the general and memory-port cases, with different rotation counts.Source: Appendix A · p. 19
Memory-port cleaning
- For memory-port cleaning, only 2w Pauli π/4 rotations are required when the Clifford acts trivially or as a CNOT control on the first w qubits.The reduced count follows from the CNOT structure and commutation with Z operators on the selected control qubits.Source: Appendix A · p. 19