LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration

Matthew Youngman; Cristian Sestito; Themis Prodromakis

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LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration

Matthew Youngman, Cristian Sestito, Themis Prodromakis

arXiv:2608.27184v1Aug 27, 2026cs.ARcs.AIcs.SE

TL;DR

LLM-based EDA systems remain fragmented across design stages and can produce plausible code without ensuring physical correctness. This perspective compares Generator, Agent, and Orchestrator roles, finding that current approaches struggle to scale to industrial designs and motivating standardised, physics-aware orchestration.

Problem
LLM-based EDA systems remain fragmented across stages, while language-model objectives can reward plausible code without ensuring physically correct hardware.
Method
The perspective defines Generator, Agent, and physically-aware Orchestrator roles and argues for cross-stage coordination linking tools, feedback, and persistent design context.
Results
Comparisons across roles show that current LLM-based EDA approaches struggle to scale from isolated tasks toward industrial designs.
Takeaways & Limitations
The paper motivates standardised orchestration that connects tools and agents across the EDA flow for more reliable and accessible hardware design.
Takeaways & Limitations
Current agentic systems and intermediate representations remain largely confined to individual design tasks and stages, limiting cross-layer understanding.

Abstract

from arXiv · show

Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verification. Large language models (LLMs) extend this trajectory by enabling direct translation from design intent to hardware implementations. In most of the EDA literature, LLM-based solutions are typically assisting siloed design stages or tasks, however this obscured the drivers by which capability emerges and systems scale. In this Perspective, we instead define three hierarchical roles that reveal how capability accumulates: a Generator that produces design artifacts in a single pass, an Agent that refines outputs through iterative tool feedback, and an Orchestrator that coordinates decisions across EDA-stages. Across published systems, this reveals a syntax trap in which models are trained to produce plausible code rather than physically correct hardware, compounded by fragmented tools and loss of design context that obscure how decisions affect later stages. Comparisons across the three roles show that current approaches struggle to scale to industrial designs, motivating a shift towards a standardised, physics-aware orchestrator that connects tools and agents across the EDA flow for more reliable and accessible hardware design.

1 Introduction

Growing chip complexity, tighter physical constraints, and shorter development windows have widened a semiconductor productivity gap, while translating engineering intent into correct, optimised hardware remains a manual bottleneck. LLMs motivate a progression from single-pass Generators and feedback-driven Agents toward physically-aware Orchestrators that coordinate EDA tools across stages.

Motivation: Chip complexity, tighter physical constraints, and shorter development windows are widening the semiconductor industry’s productivity gap.Products increasingly integrate billions of transistors and more diverse architectures, while the semiconductor market is projected to exceed $1 trillion by 2030.
Problem: Translating engineering intent into correct and optimised hardware artifacts remains manual, iterative, and dependent on scarce specialised experts.This translation bottleneck precedes automated design execution and is difficult to scale.
Motivation: LLMs can translate natural-language design intent into structured hardware artifacts because digital designs are largely expressed as HDL code, specifications, scripts, and constraint files.This makes LLM integration a natural extension of existing text-generation capabilities.
LLM roles: A Generator creates artifacts in one forward pass, whereas an Agent couples generation with automated tool feedback to repair and optimise designs within a fixed pipeline.Both roles have produced measurable gains in targeted HDL and EDA scripting, code repair, and verification tasks.
Contribution: The proposed physically-aware Orchestrator advances beyond generation and repair by adaptively selecting tools, ordering their invocation, and redirecting effort using persistent cross-stage design state.It holds control authority over the EDA pipeline itself, addressing limitations of siloed generation and fixed feedback loops.

2 The Misalignment of LLMs in the Digital Design Flow

Digital EDA translates engineering intent through increasingly abstract, automated stages, but LLMs face a syntax trap because linguistic plausibility does not ensure physical correctness. Agentic refinement and circuit-native representations improve individual tasks, yet remain disconnected across design stages and downstream physical effects.

Digital EDA Flow: EDA translates intent from NL and HLS specifications through RTL, gate-level, transistor-cell, and physical-layout abstractions, gaining productivity while reducing lower-level visibility and control.Each abstraction absorbs implementation complexity into automated tooling, producing step-changes in productivity at successive transitions 4,24–26.
The Syntax Trap: The syntax trap causes LLM-generated hardware to appear valid under shallow evaluation while failing deeper functional or physical validation.LLMs are trained by next-token prediction without a mechanism for physical correctness; 44.2% of testbench-passing designs fail formal equivalence checking.
The Syntax Trap: 55% of LLM-generated Verilog is amenable to automated repairs, while 44.2% of testbench-passing designs fail formal equivalence checking.These results quantify the gap between token-level plausibility, syntactic validity, and rigorous functional validation.
From Generation to Agentic Refinement: The field is shifting from single-pass Generators to Agents that iteratively use EDA feedback, with neuro-symbolic loops enforcing physical correctness and circuit-native intermediate representations capturing design structure 19,35,40.A debugging agent increased pass rates by more than 25 percentage points 45, but these systems remain largely confined to individual tasks and stages.
Limits of Current Approaches: Agent feedback is typically local and intermediate representations capture structure rather than downstream physical consequences, leaving decisions across abstraction levels largely disconnected.This limitation motivates cross-layer understanding and broader coordination across the digital design flow.

3 Current Applications of LLMs in EDA

Current LLM-EDA applications span 46 published systems, but their development shows rising autonomy without corresponding progress in cross-stage coordination, physical-design awareness, or evaluation beyond functional correctness. Fragmented toolchains and incompatible representations leave current remedies isolated rather than providing a unified EDA workflow.

The taxonomy maps 46 published LLM-EDA systems by function, method stack, and architectural LLM role, exposing the scope and structure of current stage-local deployments.
Decomposed systems mainly increase parallel execution rather than coordinated control because roles are fixed, handoffs are static, and workflows cannot adapt to global design state.
Autonomy increased 8.8% per year as methods progressed from ICL and RAG through domain-adapted SFT to tool-rewarded RL, but fixed reference sets limit cross-stage generalisation.RL uses hierarchical rewards from compilation, functional correctness, synthesis outcomes, and other EDA-derived signals, while remaining distribution-bound to gold designs, coverage, or benchmark baselines.
Fragmented toolchains and incompatible representations prevent reuse across systems, leaving fixes for statelessness, explainability, and coordination isolated to individual methods.Examples include HDLxGraph’s dual syntax–DFGs, CROP’s dense summary embeddings, AutoSilicon and ACE-RTL’s session persistence, RTLSquad’s decision logs, ChipSeek-R1’s reasoning traces, and MCP4EDA’s typed interface.

4 The Standardised Orchestrator

The standardised orchestrator reorganises control across nested Generator, Agent, and Orchestrator reasoning scopes, preserving design context and coordinating EDA stages. This shift depends on mature Agent-tier systems and enables measurable physical-design gains through closed-loop feedback and fast surrogates.

4 The Standardised Orchestrator: The Orchestrator has authority to choose the next step and deploy multiple agents, coordinating reasoning from individual tasks through workflows to multi-stage EDA design [fig. 3].Generator, Agent, and Orchestrator are nested scopes of reasoning, with the Orchestrator coordinating across EDA stages.
4 The Standardised Orchestrator: Standardisation becomes the prerequisite for shifting research from generation quality to coordination, with open protocols including MCP and A2A supporting that transition [31,46].Orchestration is valuable once Agent-tier systems reach sufficient maturity because tool feedback cannot compensate for a weak Generator.
4 The Standardised Orchestrator: 15–30% timing and 10–20% area improvements are reported when orchestration closes the back-end feedback loop and enables cross-layer understanding [47].The gains arise from applying orchestration across the EDA flow rather than isolating optimisation loops.
4 The Standardised Orchestrator: Orchestration preserves outputs as design context, allowing synthesis and implementation consequences to influence upstream specification and RTL decisions.Deterministic EDA tools continue enforcing correctness while neuro-symbolic feedback extends beyond isolated optimisation loops.
4 The Standardised Orchestrator: Below 2% power prediction error at more than 6× speedup is reported for physical surrogates that pre-screen poor candidates before tool use [57].These fast surrogates can reduce unnecessary expensive EDA-tool evaluations.
4 The Standardised Orchestrator: Figure 3d–e aggregates role-level Spec-to-RTL productivity across modular and system scales, where prior work reports sharp coherence degradation beyond approximately 100–150 lines of generated hardware code [37,51,52].The comparison is conditioned by the underlying model, prompting strategy, benchmark, and evaluation methodology.

5 Outlook on the Industrialized LLM

Industrial EDA is converging on standardized LLM orchestration, with deployment emerging first in contained workflow automation and PPA-driven exploration. Greater autonomy introduces substantial security risks, while standardized, traceable orchestration may also enable defensive checking and more reliable physical reasoning.

5 Outlook on the Industrialized LLM: Major EDA vendors are independently converging on orchestration through persistent design state, specialized workers, autonomous optimization loops, and auditable in-flow coordination.Cadence’s ChipStack [58], Synopsys’s AgentEngineer [59], and Siemens’ Aprisa [60] exemplify this convergence.
5 Outlook on the Industrialized LLM: 87–90% UVM coverage is now achieved by closed-loop systems, while verification leads deployment because correctness signals are cheap and failures are contained.Verification represents roughly 47% of engineering effort [62], and industrial deployments report order-of-magnitude reductions across RTL generation, simulation, and formal verification [63].
5 Outlook on the Industrialized LLM: Parallel specialized workers enable PPA-driven design-space exploration by pursuing competing hypotheses simultaneously and compressing optimization cycles that previously required extensive manual synthesis effort [10,64].This shift makes HDL development and EDA scripting less central to productive hardware development.
5 Outlook on the Industrialized LLM: Attack success exceeds 90% against defensive detection of only 25–35%, exposing risks from prompt-injected Trojans, cloud-based intellectual-property leakage, and unchecked functional or side-channel flaws.These risks accompany the broader generative autonomy represented by automated security probing.
5 Outlook on the Industrialized LLM: Directed orchestration can counter these risks through information-flow tracking, adversarial fuzzing, and provenance traces that expose Trojan sites and illegal states before deployment [8].Richer intermediate representations and emerging world models may further improve physical reasoning as chiplets and 3D integration increase design interactions.

Supplementary Information

The supplementary information provides a taxonomy of LLM-for-EDA systems and pooled specification-to-RTL estimates across correctness, PPA, time-to-solution, and cost. Orchestrators show lower system PPA than agents, while projected verification performance is highest but slower and more expensive than generators.

Taxonomy: Table 1 manually codes LLM-for-EDA papers by function, method, stack, role, autonomy, explainability, and evaluation focus, with ordinal dimensions ranked by capability.The taxonomy covers papers released from 2023–2026 and records each paper’s first public release date.
Pooled system estimates: 0.925 × system PPA for the orchestrator is lower than the agent’s 1.025 × estimate on MCP4EDA.Both values use Claude 4 Sonnet and the geometric mean of area and delay.
Pooled system estimates: 90 % projected system verification integration for the orchestrator exceeds the generator’s 87.1 % and the agent’s 80.0 %.The orchestrator value is projected from architectural capability, whereas the generator and agent values are benchmark estimates.
Pooled system estimates: 13.4 s is the generator’s system time-to-solution, compared with 300 s for the agent and 138 s for the orchestrator.The table also lists a human estimate of 300 s as a conservative lower bound.
Pooled system estimates: System cost per design is $0.055 for the generator, $0.21 for the agent, and $0.587 for the orchestrator.The human reference is $0.000 because it is definitional and assumes no API cost.