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LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation

Shu Gu, Matthew Youngman, Yuqin Zhao, Cristian Sestito, Ali Siddique, Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis

arXiv:2610.16625v1cs.AI

TL;DR

Post-route FPGA timing closure is costly and expert-dependent. LATCH separates LLM orchestration from deterministic execution and compares action-control levels and iterative search strategies. Expert recipes are more reliable than freer controls, while branching and knowledge-base guidance improve mean gains over sequential reasoning.

  • Problem

    Post-route timing closure depends on design-specific physical expertise and can require full placement-and-routing runs lasting hours or days.

    Source: §I · p. 1

  • Method

    LATCH separates LLM orchestration from deterministic FPGA analysis, implementation, validation, and measurement, then compares action-control levels and multi-iteration search strategies.

    Source: §I · p. 2

  • Results

    Within twelve DCPs, mean improvement rose from 10.5% (sequential) to 16.0% (branching) and 20.3% (knowledge base), matching the fitted heuristic’s 19.9%.

    Source: §V · p. 13

  • Takeaways & Limitations

    Iterative recipe selection exceeded the best single-recipe attempt on all sixteen designs and the best direct-operation attempt on eleven, with one tie.

    Source: §IV · p. 12

Abstract

from arXiv · show

Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation. Across sixteen designs and seven LLMs, a single-iteration study compares three agent control granularities - expert-written recipes, direct EDA operations and LLM-constructed procedures - to ask how much control an agent needs per attempt. Functional-pass rates are 98.2%, 71.4% and 17.9%, respectively; yet direct operations give slightly larger 3.4% median Fmax gains when passing, versus 3.2% for recipes. This exposes a trade-off between execution reliability and timing improvement. Informed by this trade-off, a multi-iteration study fixes the action tier at expert recipes to ask how repeated attempts are best organised, comparing a fitted deterministic heuristic with sequential LLM reasoning, branching exploration and knowledge base-guided exploration within 12 checkpoints per run. Branching raises mean maximum-frequency improvement from 10.5% (sequential) to 16.0%, and the knowledge base to 20.3%, improving 15 of 16 designs. Characterisation across 2,421 recipe attempts profiled their gain and validation rates, showing hard-block re-placement gives the largest cumulative mean gain at 41.4MHz.

I. INTRODUCTION

Post-route FPGA timing closure is costly and depends on design-specific physical expertise. LATCH separates LLM orchestration from deterministic execution and evaluates control freedom and search strategies for FPGA timing optimisation.

I. INTRODUCTION

  • Timing closure requires design-specific physical interventions and can require full placement-and-routing runs lasting hours or days.Interventions include changes to placement, routing, physical optimisation, or constraints.Source: §I · p. 1
  • Prior autotuners remove manual tuning but remain tied to costly implementation iterations and generalise poorly to unseen designs.Learned placement-policy generalisation across designs remains an open research problem.Source: §I · p. 1
  • Backend LLM agents face a syntax trap: plausible textual, script, or RTL outputs can be physically ineffective, unsafe, or disconnected from implementation behaviour.Physical-design data is scarce, licensed, and expensive to generate, while benchmarks report difficulties with geometric reasoning, PPA trade-offs, and long tool workflows.Source: §I · p. 1
  • LATCH separates LLM orchestration from deterministic implementation, validation, and measurement to study LLM decision-making in backend EDA.The framework is introduced as a reproducible approach to post-route FPGA Fmax improvement.Source: §I · p. 2
  • LATCH compares three control granularities, then fixes expert recipes to compare branching and knowledge-base guidance with sequential reasoning and a fitted heuristic.The studies use sixteen designs, with seven LLMs in the single-iteration study and three in the multi-iteration study.Source: §I · p. 2

II. METHODOLOGY

LATCH uses a deterministic backend and an LLM orchestration layer to select and evaluate modifications to post-route FPGA checkpoints. Its run state retains validated checkpoints and records search history and recipe knowledge.

II. METHODOLOGY

  • LATCH separates deterministic analysis, modification, and measurement from an orchestration agent that selects modifications using backend evidence.The layers communicate as servers through the Model Context Protocol.Source: §II · p. 2, Figure 1 · p. 3

1) Inputs and outputs:

  • Each optimisation step starts from a retained DCP and produces one candidate, which joins the retained set only after passing validation.The run also stores search history and a knowledge base of design-independent recipe notes distilled from exhaustive offline trials.Source: 1) Inputs and outputs · p. 3

2) The optimisation step:

The optimisation loop gathers evidence, selects an action, executes it deterministically, and validates the resulting checkpoint. Search can proceed sequentially or branch across retained checkpoints under a fixed run budget.

2) The optimisation step:

  • Action selection ranges from choosing a fixed expert recipe, to specifying direct EDA operations, to constructing bounded targeting procedures.All three control levels compile to a fixed set of Vivado and RapidWright commands, which the backend applies deterministically.Source: 2) The optimisation step · p. 3

3) Validation, comparison, and search update:

  • Validation checks candidate legality, remeasures timing, and compares the result with its parent; invalid or regressive candidates are recorded but not expanded.A valid candidate returns to the search space and may become a later parent.Source: 3) Validation, comparison, and search… · p. 3
  • Sequential search expands one retained checkpoint at a time, whereas branching keeps multiple checkpoints on the frontier and may expand several within the run budget.The scheduler ranks legal checkpoint–action pairs across the frontier to select the next parent.Source: 3) Validation, comparison, and search… · p. 3
  • The illustrated branching pattern tries alternatives from a shared checkpoint, and an invalid attempt leaves its parent available.The run history records applied changes and measured outcomes; the figure’s numerical values illustrate the workflow, not experimental results.Source: Figure 2 · p. 4
  • A run’s checkpoint budget and branching depth, expansion, and concurrency are fixed in advance, and its recorded outcomes support inspection, resumption, or reproduction.All multi-iteration levels receive a maximum budget of twelve DCPs per benchmark run.Source: 3) Validation, comparison, and search… · p. 4

B. The Deterministic Execution Backend

The deterministic backend controls analysis, execution, checkpoint generation, and timing evaluation, while the agent proposes operations. Its diagnostic evidence links timing failures to physical characteristics of the design.

B. The Deterministic Execution Backend

  • The backend controls analysis, execution, checkpoint generation, and timing evaluation, so performance depends on commands that change the DCP’s physical implementation.Expert recipes are fixed procedures embedding engineering expertise; finer action tiers are generated by the agent from the same EDA operations.Source: B. The Deterministic Execution Backend · p. 4

1) Design analysis and diagnostic extraction:

  • Before optimisation, Vivado extracts WNS, TNS, and failing endpoints from the timing summary and queries the clock period and achievable operating frequency.The analysis is performed deterministically on the input implementation.Source: 1) Design analysis and diagnostic… · p. 4
  • Physical diagnostics measure critical-path cell spread and routing detour; high spread motivates region-constrained placement, while large detours identify candidates for cell re-placement.The diagnostic set also includes critical high-fanout nets, critical-path information, and timing measures.Source: 1) Design analysis and diagnostic… · p. 4

2) Expert optimisation recipes:

Expert recipes package known procedures for timing bottlenecks, while the framework evaluates routed timing and varies what the agent returns at each control level.

2) Expert optimisation recipes:

  • Each expert recipe applies a fixed sequence of examination, modification, implementation, and evaluation operations for one class of timing bottleneck.Selecting a recipe commits the agent to a known procedure rather than an arbitrary tool invocation.Source: 2) Expert optimisation recipes · p. 4
  • Seven recipes modify designs inside Vivado, while fanout and lut_cone edit netlists in RapidWright and lack an intermediate improvement guarantee.Validation risk concentrates almost entirely in those two recipes.Source: 2) Expert optimisation recipes · p. 5

3) Timing verification and quantitative feedback:

  • Positive ∆WNS and ∆Fmax indicate improvement, and Fmax is recalculated after routing against the baseline.The objective continues rewarding improvement after timing is met; runs do not terminate at WNS ≥0.Source: 3) Timing verification and… · p. 5

C. The LLM Agent Orchestration Layer

  • At the recipe interface, the agent ranks catalogue choices; at direct-operation and constructed-procedure interfaces, it submits executable proposals that can be revised after feedback.Fig. 3 depicts the prompt's variable design state, diagnosis, and control interfaces alongside a fixed template and a response ending in a ranked list and selected action.Source: C. The LLM Agent Orchestration Layer · p. 5, Figure 3 · p. 5

1) Prompt construction:

The prompt supplies design evidence and available actions, while a knowledge base and bounded probes support recipe selection during multi-iteration search.

1) Prompt construction:

  • The fixed prompt combines timing, critical-path, and placement evidence with the task and actions available at the active control level.The agent ranks recipe candidates by priority and risk; a deterministic rule selects among them, excluding recently applied or attempted recipes.Source: 1) Prompt construction · p. 5
  • The agent states evidence and uncertainty when scoring recipe candidates, leaving a traceable record of its rationale.The recorded reasoning may prove wrong.Source: 1) Prompt construction · p. 6

2) The knowledge base:

  • Each knowledge-base entry describes a recipe’s mechanism, conditions under which it may help or hurt, and achievable ceiling, based on offline executions across known designs.The entries generalize findings qualitatively because numeric thresholds measured on one checkpoint rarely transfer to another.Source: 2) The knowledge base · p. 6
  • Knowledge-base entries are labelled as prior evidence, supplying vendor-specific timing-closure knowledge as in-context learning rather than evidence about the current design.The paper notes that this expertise resides largely in vendor-specific interfaces and engineering experience unlikely to appear in training data.Source: 2) The knowledge base · p. 6

3) Deep analysis and the bounded decision loop:

  • When a violation remains ambiguous, the agent can use read-only probes to refine its description of the current DCP without creating a new design state.Ten probes cover reports, stored search evidence, and broader search history; fewer are offered at ordinary checkpoints and after validation failure.Source: 3) Deep analysis and the bounded… · p. 6
  • Probe use is capped at six commands for the root decision and four at other DCP steps, with a fixed neutral-priority ordering substituted if the agent returns no ranking.A sweep with a raised bound reduced substitution below 1% without improving achieved frequency.Source: 3) Deep analysis and the bounded… · p. 6

4) Validation and recovery:

Candidates undergo structural validation, while simulation-based functional checking is reserved for the selected result.

4) Validation and recovery:

  • Every candidate must pass structural validation, while functional checking tests the selected published result against the starting design.Structural checks confirm the checkpoint reopens, routing completes without errors or unrouted nets, and timing is measurable; functional checks use a precheck and five deterministic simulations of 200 input vectors each. Failed, regressing, or infeasible candidates are excluded and the search reverts to the parent checkpoint.Source: 4) Validation and recovery · p. 6

A. Benchmark and Experimental Constraints

The evaluation spans post-route designs with varied scale, resource mix, timing slack, and development or held-out status.

A. Benchmark and Experimental Constraints

  • The benchmark set contains sixteen post-route DCPs spanning approximately 3k to 325k LUTs and FFs, with baseline frequencies from 406 MHz to 48.2 MHz.Fifteen designs come from FPL 2026 AMD Competition benchmarks and one from RapidWright; resource mixes include soft-logic-, memory-, and arithmetic-dominated designs.Source: A. Benchmark and Experimental… · p. 6
  • The benchmark selection spans timing slack, but some designs have substantial frequency yield while others are constrained by logic depth or hard-block delay.The lowest-frequency design has WNS of −19.2 ns, while the highest-frequency design has WNS under 1 ns.Source: A. Benchmark and Experimental… · p. 6
  • Eight known designs form the development set, while five family re-implementations and three out-of-family designs form the eight held-out designs.This split applies to the multi-iteration study; the single-iteration study uses all sixteen designs and no knowledge base.Source: A. Benchmark and Experimental… · p. 6

B. Single-Iteration Agent Control Study

Across 16 designs and seven LLMs, the study compares recipe selection, direct EDA operations, and constructed procedures to examine reliability and timing gain. The effects of additional control vary by design and model.

B. Single-Iteration Agent Control Study

  • Each design-model pair starts from a shared checkpoint across the three conditions, with at most one proposal executed and scored and no revision using measured candidate timing.The study includes 112 trials per condition and uses no knowledge base.Source: B. Single-Iteration Agent Control Study · p. 7
  • 98.2% (110/112) of recipe trials, 71.4% (80/112) of direct-operation trials, and 17.9% (20/112) of constructed-procedure trials pass; passing direct operations yield +3.4% median Fmax improvement versus +3.2% for recipes.Recipes improve timing in 91 of 112 assigned trials, compared with 67 for direct operations.Source: B. Single-Iteration Agent Control Study · p. 7, Figure 5 · p. 7
  • Of 20 passing constructed-procedure trials, 10 show no change, eight regress, and only two improve timing.The constructed-procedure median improvement is 0%.Source: B. Single-Iteration Agent Control Study · p. 7
  • Direct operations qualify 111 of 112 proposals, execute 81, pass 71, and improve timing in 60; constructed procedures qualify 25, execute and pass 19, and improve timing in one.Constructed procedures lose most trials before a qualifying proposal; Claude Sonnet 5 passes 13 constructed-procedure trials but improves none.Source: B. Single-Iteration Agent Control Study · p. 8
  • On vexriscv_re-place, direct operations raise GPT-5.6 Sol’s gain from +31.5% to +37.4% but reduce DeepSeek v4 Pro’s from +31.5% to +23.8%; on boom_soc, only two models pass with direct operations.All seven models pass on boom_soc with recipes; the two direct-operation passes have gains similar to their recipe results.Source: B. Single-Iteration Agent Control Study · p. 8, Figure 7 · p. 8
  • On LogicNets, DeepSeek v4 Flash gains +117.0 MHz with direct operations versus +98.0 MHz for the best recorded recipe; on FINN RadioML, GPT-5.6 Sol gains +66.1 MHz as the limiting path shifts to RAM blocks.On vexriscv_re-place, DeepSeek v4 Pro’s lower logic delay is outweighed by routing delay increasing from 1.840 to 2.160 ns.Source: B. Single-Iteration Agent Control Study · pp. 8–9, Table III · p. 8

C. Multi-Iteration, Expert Recipes Ablation Study

The multi-iteration study fixes execution at expert recipes and varies how recipes are selected. Knowledge base-guided exploration achieves the highest reported mean improvement, while model-driven levels improve most designs, including held-out benchmarks.

C. Multi-Iteration, Expert Recipes Ablation Study

  • The study holds the nine expert recipes and validation gating fixed, comparing a fitted heuristic with sequential, branching, and knowledge base-guided selection under a 12-DCP budget.The three LLM-based levels form an inclusion chain, adding branching and then knowledge base guidance.Source: C. Multi-Iteration, Expert Recipes… · p. 9
  • 20.3% mean improvement for knowledge base-guided exploration exceeds 16.0% for branching and 10.5% for sequential reasoning; the fitted heuristic reaches 19.9%.The three model-driven levels return positive gains on 14, 16, and 15 of 16 designs, respectively.Source: C. Multi-Iteration, Expert Recipes… · p. 10
  • Held-out examples include a 124.7 MHz gain on AMD mini-ISP, while the fitted heuristic returns no improvement on five of eight held-out designs.The knowledge base-guided BOOM SoC run gains 49.3 MHz; every ablation has a higher mean on development designs than held-out designs, including 28.6% versus 11.9% for knowledge base guidance.Source: C. Multi-Iteration, Expert Recipes… · p. 10
  • About 68% of a design’s best observed result is reachable within one intervention, and evaluating three openings adds approximately +8.6 MHz over a single opening.Beyond the opening candidates, 34.4% of physically valid improvement attempts produce no further gain, versus 9.2% among opening candidates; repeated phys_opt falls from approximately +22 MHz to under +5 MHz.Source: C. Multi-Iteration, Expert Recipes… · p. 10
  • The fitted heuristic concentrates 77% of attempts on two high-yield recipes, compared with 0.6% for sequential reasoning and 11% for branching; knowledge base guidance raises this to 21%.Hard-block re-placement is the best-performing recipe on six of sixteen designs, but its scope depends on surrounding logic and placement.Source: C. Multi-Iteration, Expert Recipes… · p. 10, Figure 9 · p. 11
  • Hard-block re-placement has little scope on picoblazearray, whose 660 small cores already sit beside memory blocks; auto_pblock fails on over 89% of attempts on four designs.auto_pblock reliably fits twelve designs, while its risk on the other four is whether the design fits the region.Source: C. Multi-Iteration, Expert Recipes… · p. 11
  • Four recipes confined to Vivado passed all 1,477 attempts, while the RapidWright-exporting fanout and lut cone recipes passed 38.2% and 76.4%.Validation rejected a partially placed auto_pblock result that reported a 105 MHz gain.Source: C. Multi-Iteration, Expert Recipes… · p. 11
  • Branching and knowledge base-guided exploration average 1.66× and 1.69× phase-time-to-wall-time ratios, below the ideal 3.0×; tool execution and diagnostics account for 91–92% of phase time.Across the three LLMs, median language-model cost varies roughly twentyfold while mean improvement differs by under a percentage point.Source: C. Multi-Iteration, Expert Recipes… · p. 11, Figure 10 · p. 11

IV. DISCUSSION

The discussion contrasts one-shot action breadth with iterative recipe search: direct operations often win per design, but iterative recipes generally surpass them. It frames deployment as recipe-first escalation while identifying transfer and validation boundaries.

IV. DISCUSSION

  • Direct operations matched or beat the best recipe result on 14 of 16 designs, while iterative recipes beat the best single recipe on all 16 and the best direct attempt on 11.The four remaining direct-operation wins were narrow, ranging from 1.3 to 4.9 percentage points.Source: §IV · p. 12
  • About 68% of a design’s best observed result was reachable in one intervention, supporting recipe-first escalation when a measured bottleneck remains unresolved.The discussion says further study should determine which design evidence should trigger a change in control and how to divide the remaining budget.Source: §IV · p. 12
  • The recipe catalogue is weighted toward placement and routing, while logic-focused additions would require formal or broader equivalence checking beyond sampled simulation.Structural and functional validity alone does not ensure a frequency gain across a tool boundary, so commit-only-if-improved checks should be reapplied there.Source: §IV · p. 12
  • The harness evidence is bounded by one device family, toolchain, tool version, and a knowledge base distilled from eight known designs.Testing transfer requires larger benchmark sets, other vendors, and independently constructed or continuously updated knowledge bases.Source: §IV · p. 12

V. CONCLUSION

LATCH separates LLM orchestration from deterministic execution for post-route FPGA frequency improvement. Across sixteen designs, recipes were more reliable in single attempts, while branching and knowledge-base-guided recipe search improved multi-iteration results.

V. CONCLUSION

  • Within twelve DCPs per run, mean improvement rose from 10.5% with sequential reasoning to 16.0% with branching and 20.3% with a knowledge base, matching the fitted heuristic’s 19.9%.Source: §V · p. 13
  • In single attempts, expert recipes passed functional checks in 98.2% of trials, direct EDA operations in 71.4%, and constructed procedures in 17.9%.Passing direct operations had a +3.4% median gain, versus +3.2% for expert recipes.Source: §V · p. 13
  • Per-design best gains ranged from 0.4% to 102.2%, with iterated recipe selection producing the best result on twelve designs and one direct-operation attempt on four.Source: §V · p. 13

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