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AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies
Jian Gao, Weidong Cao, Junyi Yang, Xuan Zhang
TL;DR
Analog IC topology generation is hindered by limited datasets and inadequate representations, despite the importance of accelerating IC design. AnalogGenie combines a comprehensive topology dataset with a scalable sequence-based pin-level graph and GPT generation, reporting diverse, large, valid, high-performance, and unseen topologies across benchmarks. The framework’s current sizing algorithm remains a sample-efficiency improvement target.
Problem
Analog topology generation lacks comprehensive data and scalable, unambiguous representations, while analog design remains difficult to abstract and automate.
Method
AnalogGenie uses a domain-specific GPT model that predicts the next device pin over augmented Eulerian sequences derived from pin-level circuit graphs.
Results
Experiments across three analog circuit benchmarks efficiently discover previously unseen topologies at scale, with reported improvements in variety, design size, validity, and performance.
Takeaways & Limitations
AnalogGenie demonstrates a scalable generative approach for automatic analog topology discovery beyond conventional small-scale generation settings.
Takeaways & Limitations
The current sizing algorithm is effective but its sample efficiency can be improved with more advanced alternatives.
Abstract
from arXiv · showhide
The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing. Excitingly, recent studies have shown the great capabilities of foundational models in expediting the design of digital ICs. Yet, applying generative AI techniques to accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits. This paper proposes, $\textbf{AnalogGenie}$, a $\underline{\textbf{Gen}}$erat$\underline{\textbf{i}}$ve $\underline{\textbf{e}}$ngine for automatic design/discovery of $\underline{\textbf{Analog}}$ circuit topologies--the most challenging and creative task in the conventional manual design flow of analog ICs. AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits. Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the number of devices within a single design, and discovering unseen circuit topologies far beyond any prior arts. Our work paves the way to transform the longstanding time-consuming manual design flow of analog ICs to an automatic and massive manner powered by generative AI. Our source code is available at https://github.com/xz-group/AnalogGenie.
1 INTRODUCTION
Analog IC design remains difficult to automate because analog circuits lack systematic hierarchical representations and require heuristic, knowledge-intensive manual design. AnalogGenie addresses these gaps with a comprehensive topology dataset and scalable sequence-based graph representation for broad, large, and unseen topology generation.
- Motivation: Analog ICs resist the abstraction methods and high-level languages that support automated digital IC design.Analog design lacks systematic hierarchical representation and remains heuristic and knowledge-intensive.
- Motivation: Manual analog design includes time-consuming topology selection or creation followed by device-parameter optimization.
- AnalogGenie: AnalogGenie targets scalable, general analog topology generation beyond methods limited to single, small-size, or conventional circuit types.The paper reports broader variety, more devices per design, and unseen topology discovery.
- Dataset: More than 3000 distinct analog circuit topologies spanning diverse functionalities form AnalogGenie’s comprehensive dataset.Examples include Op-Amps, LDOs, bandgap references, comparators, PLLs, LNAs, power amplifiers, mixers, and VCOs.
- Representation: AnalogGenie represents each topology as a pin-level graph sequentialized into an Eulerian circuit, enabling scalable and unambiguous generation.Each graph node is a device pin, and the Eulerian trail visits every edge exactly once while starting and ending at the same node.
- Contributions: The contributions combine a GPT-based next-device-pin generator, sequence-based pin-level representation, comprehensive data with augmentation, and experiments reporting valid unseen topologies.
2 PRELIMINARIES AND RELATED WORKS
Analog topology design can use graph or SPICE-netlist representations, but existing approaches face limits in scalability, data availability, and low-level connection fidelity. These constraints motivate AnalogGenie’s topology-focused dataset and representation choices.
- Analog design flow: Topology construction determines device types, device counts, and interconnections before sizing and physical layout.
- Graph representations: Graph generation maps nodes to devices and edges to connections, but prior one-shot adjacency-matrix methods often target only one circuit type.
- SPICE representations: SPICE netlists provide text-based device-connection descriptions for simulation, yet publicly accessible netlist data is much scarcer than topology illustrations.
- SPICE representations: High-level text representations can make topology generation error-prone because multiple tokens may describe a single device connection.
- Dataset gap: Existing circuit datasets are often restricted to specific circuit types and lack labels such as circuit performance.
3 APPROACH
AnalogGenie combines a pin-level graph, Eulerian sequence representation, augmentation, and a domain-specific GPT model to generate analog topologies. The approach targets sparse, large, permutation-invariant circuit data while supporting diverse circuit types and fine-tuning.
- Approach: AnalogGenie models each device pin as a graph node and sequentializes large sparse circuit graphs for scalable topology generation.The representation explicitly captures every device interaction and connection.
- Pin-level representation: Device-level graphs can map ambiguously to circuit topologies, whereas pin-level graphs explicitly identify every connection with a unique mapping.
- Scalability: Adjacency matrices waste space for sparse analog graphs because they store O(n^2) entries despite far fewer edges.The paper gives a six-node, six-undirected-edge example whose 6×6 matrix wastes 24 elements on absent edges.
- Sequential representation: An Eulerian circuit visits every edge exactly once and returns to its starting node, providing the sequence structure used for topology representation.
- Sequential representation: The Eulerian construction can represent any topology modeled as a finite connected undirected graph after bidirectional edge conversion.
- Data augmentation: AnalogGenie augments real-world circuits with multiple Eulerian representations, generating 70× more data while addressing permutation invariance.
- Model training: A customized tokenizer and complete-topology pre-training train the GPT model to predict the next device pin, followed by fine-tuning for target high-performance circuits.
4 RESULTS
AnalogGenie is evaluated on dataset scale, augmentation, correctness, scalability, novelty, and circuit performance against established analog-topology generators. Results show that augmentation and its pin-level sequential representation support broader, larger, more novel, and more capable circuit generation.
- Experiment setup: The dataset contains 3,350 distinct topologies across 11 circuit types, with the largest circuit comprising 54 devices.Training uses a 9:1 train-validation split and expands the sequences 70× through augmentation.
- Data augmentation: Augmentation reduces validation loss by approximately 8.5× and increases the number of valid circuits by 73.5×.The comparison uses 3,015 unaugmented sequences versus 227,766 augmented sequences; unaugmented training otherwise led to overfitting and invalid generations.
- Correctness: AnalogGenie reaches 73.5% valid circuits after pretraining and 93.2% after fine-tuning, exceeding AnalogCoder, CktGNN, and LaMAGIC.The baselines achieve 57.3%, 67.5%, and 68.2% valid circuits, respectively.
- Scalability: AnalogGenie generates 11 circuit types and circuits with up to 64 devices after pretraining or 56 after fine-tuning.Its sequential representation and dataset support larger designs than the baselines, whose reported limits range from 10 to 22 devices, while LaMAGIC uses four device nodes.
- Novelty: AnalogGenie generates nearly 100% novel circuits, compared with 93.1% for CktGNN, 12.7% for LaMAGIC, and 8.9% for AnalogCoder.The paper evaluates novelty by comparing generated topologies against those already present in the dataset.
- Performance: Fine-tuning raises AnalogGenie’s Op-Amp FoM from 19 to 36.5, power-converter FoM from 2.5 to 3.3, and bandgap-reference FoM from 17.2 to 21.9.AnalogGenie is the only compared model reported to design bandgap reference circuits.
5 CONCLUSION AND FUTURE WORK
AnalogGenie combines a GPT-based topology generator with parameter optimization to discover diverse and previously unseen analog circuit topologies. The authors identify improved sizing efficiency and digital-circuit integration as future directions.
- AnalogGenie generates analog circuits by predicting the next device pin to connect within a circuit.
- Experiments across three analog circuit benchmarks show scalable discovery of previously unseen circuit topologies.
- The framework combines topology discovery with a genetic algorithm for optimizing parameters such as sizing and bias.
- The current sizing algorithm is effective, but its sample efficiency could be improved with more advanced alternatives.
- Future work considers combining AnalogGenie’s graph generation with code generation to enhance digital circuit development.
6 REPRODUCEBILITY STATEMENT
The reproducibility statement identifies the paper’s theoretical, implementation, software, simulation, and dataset resources. These materials include the genetic-algorithm sizing framework and Ngspice infrastructure.
- The paper identifies Theorem 3.2.1 as its main theoretical backbone and places its proof in Section 3.2.
- Experiment setup and implementation details are discussed in Section 4.1.
- Supplementary materials provide code for data augmentation, pretraining, finetuning, genetic-algorithm sizing, and Ngspice simulation.
- The authors provide an open-sourced circuit dataset.
A.1 DATASET STATISTICS
The appendix presents dataset statistics through distributions of device counts and circuit topology types. These figures characterize the composition of the analog circuit dataset.
- Figure 5 presents the device number distribution in the analog circuit dataset.
- Together, the figures characterize dataset composition along device-count and topology-type dimensions.
- Figure 6 presents the circuit topology type distribution in the analog circuit dataset.
A.2 TOKENIZER LOOKUP TABLE
The tokenizer lookup table maps devices to indices and includes both basic devices and multi-device logic gates. This supports sequence encoding for larger mixed-signal circuits.
- It represents basic devices such as NMOS and PMOS.
- It also represents multi-device logic gates such as INV and XOR.
- Including logic gates allows the representation to scale to large digital circuits for mixed-signal circuit construction.
- The lookup table provides device-to-index mappings used by the tokenizer.
A.3 MORE DETAILS ABOUT EULERIAN CIRCUIT AND DATA AUGMENTATION
AnalogGenie represents analog circuit topologies at the device-pin level and uses Eulerian circuits to compactly encode them while supporting data augmentation through DFS-based traversal permutations.
- Representation: A two-device circuit produces a 14-node device pin level graph, making an adjacency matrix substantially larger than an Eulerian circuit representation.The passage reports 14 × 14 = 256 adjacency-matrix elements versus 43 Eulerian-circuit elements, around 5.95× smaller.
- Representation: 43 elements encode the example Eulerian circuit, compared with 14 × 14 = 256 elements for its adjacency matrix representation.
- Data augmentation: Permuting the DFS neighbor-exploration order generates unique Eulerian circuits for data augmentation.
- Data augmentation: Figure 7 presents the circuit topology, its device pin level graph representation, and four unique Eulerian circuits found using DFS.
A.4 ANALOGGENIE’S GENERATED CIRCUIT TOPOLOGY VISUALIZATION
This section visualizes novel circuits generated by AnalogGenie and demonstrates zero-shot generation for a circuit type absent from the dataset, with examples manually drawn in Cadence Virtuoso.
- Visualization: The authors manually draw generated circuit examples in Cadence Virtuoso, an industry-standard analog schematic edit tool, to visualize their schematics.
- Generated circuits: The generated Op-Amp example has GBW = 12 MHz, CL = 100 pF, Power = 32.88 mW, and FoM = 36.5.
- Generated circuits: The generated DC converter example has Efficiency = 0.95, Voltage conversion ratio = 2.35, and FoM = 3.3.
- Generated circuits: The generated bandgap reference example has TC = 3 ppm/◦C, Line regulation = 0.196 %/V, PSRR = 70 dB, and FoM = 21.9.
- Zero-shot generation: AnalogGenie generates a transconductance amplifier zero-shot even though that circuit type is not included in the dataset.
- Failure cases: Figures 12 and 13 provide two failed examples from AnalogGenie’s generated circuits.