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AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies

Jian Gao, Weidong Cao, Junyi Yang, Xuan Zhang

arXiv:2503.00205v1cs.LGcs.AR

TL;DR

Analog circuit generation remains constrained by gaps in comprehensive topology data and scalable, unambiguous circuit representations. AnalogGenie combines a topology dataset and sequence-based graph representation with GPT-based generation, producing more diverse, large-scale, valid, unseen, and high-performance topologies than prior graph-generation and foundation-model work.

  • Problem

    Analog-circuit generation lacks a comprehensive topology dataset and scalable, unambiguous representations, limiting research on general and scalable design.

    Source: §1 · p. 2

  • Method

    AnalogGenie uses a GPT model to predict device-pin connections, supported by a pin-level sequence graph representation and a comprehensive topology dataset.

    Source: §1 · p. 3, §3 · p. 4

  • Results

    AnalogGenie generates far more large-scale, valid, unseen, and high-performance topologies than existing graph-generation and foundation-model work.

    Source: §1 · p. 3

  • Takeaways & Limitations

    Across three analog-circuit benchmark types, AnalogGenie efficiently discovers previously unseen topologies in a scalable manner.

    Source: §5 · p. 9

    The sizing algorithm is effective, but its sample efficiency can be improved with more advanced alternatives.

    Source: §5 · p. 10

Abstract

from arXiv · show

The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing. Excitingly, recent studies have shown the great capabilities of foundational models in expediting the design of digital ICs. Yet, applying generative AI techniques to accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits. This paper proposes, $\textbf{AnalogGenie}$, a $\underline{\textbf{Gen}}$erat$\underline{\textbf{i}}$ve $\underline{\textbf{e}}$ngine for automatic design/discovery of $\underline{\textbf{Analog}}$ circuit topologies--the most challenging and creative task in the conventional manual design flow of analog ICs. AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits. Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the number of devices within a single design, and discovering unseen circuit topologies far beyond any prior arts. Our work paves the way to transform the longstanding time-consuming manual design flow of analog ICs to an automatic and massive manner powered by generative AI. Our source code is available at https://github.com/xz-group/AnalogGenie.

1 INTRODUCTION

Analog IC design remains difficult to automate because it lacks systematic hierarchical representations and depends on heuristic, knowledge-intensive topology design. AnalogGenie addresses this challenge with a scalable approach to discovering analog circuit topologies.

Introduction

  • Topology generation is the creative foundation of a time-consuming manual analog-design flow, which also includes device-parameter optimization and physical-layout design.Analog circuits resist digital-style abstraction because they lack systematic hierarchical representations and their design is heuristic and knowledge-intensive.Source: §1 · pp. 1–2
  • CktGNN generates Op-Amp topologies, LaMAGIC targets power converters with fewer than four devices, and AnalogCoder generates PySpice code for conventional circuits typically around ten devices.The introduction characterizes prior methods as limited in generation scale or circuit variety; it also says fixed-node graph representations omit low-level details and high-level text can make connections error-prone.Source: §1 · p. 2
  • The dataset contains more than 3,000 distinct analog topologies across diverse functions and is expanded by over 70× through data augmentation.Examples include Op-Amps, LDOs, bandgap references, comparators, PLLs, LNAs, power amplifiers, mixers, and VCOs.Source: §1 · p. 2
  • AnalogGenie represents each topology as an undirected graph of device pins, then sequentializes it into an Eulerian circuit that traverses each edge once and returns to its start.The paper presents this sequence-based, pin-level representation as a scalable and flexible way to describe large circuit graphs.Source: §1 · pp. 2–3
  • AnalogGenie is a GPT-based engine that predicts the next device pin to connect and is presented as generating diverse, large-scale, valid, unseen, and high-performance topologies.The paper describes these capabilities as exceeding existing graph-generation and foundation-model approaches.Source: §1 · pp. 2–3

2 PRELIMINARIES AND RELATED WORKS

Analog circuit topology design is the most creative stage of analog IC design, yet remains difficult to automate. The paper motivates scalable graph generation and a broad, labeled dataset as ways to address this challenge.

2.1 DESIGN PROCESSES OF ANALOG CIRCUITS

  • Analog circuit design proceeds from topology creation to device sizing and physical layout, with topology design demanding the most creative effort because it must be conceptualized from scratch.Automation has advanced for sizing (Wang et al., 2020; Cao et al., 2022; Cao et al., 2024) and layout, but topology generation remains challenging.Source: §2.1 · p. 3

2.2 GENERATIVE AI FOR ANALOG CIRCUIT TOPOLOGY GENERATION

  • Graph generation maps devices and their connections to nodes and edges, while prior one-shot methods and text-based netlist generation face scalability and reliability limits.Prior graph methods such as CktGNN (Dong et al., 2023) and LaMagic (Chang et al., 2024) target limited circuit types and predefine node counts; AnalogCoder (Lai et al., 2024) uses PySpice netlists, and even GPT-4 struggles with simple circuits under 10 devices. The paper therefore uses sequential graph generation, with one action per step rather than multiple code tokens per device or connection.Source: §2.2 · pp. 3–4

2.3 OPEN-SOURCE ANALOG CIRCUIT DATASETS

  • The authors created a dataset of 3,350 distinct analog circuit topologies spanning diverse functions, with manually drawn schematics and performance-metric labels.Existing datasets often focus on Op-Amps, lack performance labels, and contain non-unique designs derived from permuted templates.Source: §2.3 · p. 4

3 APPROACH

AnalogGenie combines a pin-level graph representation, Eulerian-circuit sequences, data augmentation, and a customized GPT workflow to generate analog circuit topologies. Its approach targets explicit circuit connectivity, scalable representation, and more robust learning from real-world circuits.

3.1 EXPRESSIVENESS-ENHANCED GRAPH REPRESENTATION FOR TOPOLOGY MODELING

  • Representing each device pin as a node in a connected undirected graph makes circuit connections explicit and avoids the ambiguity and topology limits of prior device-level DAG representations.The pin-level representation provides a unique mapping between each graph and circuit topology.Source: §3.1 · p. 5, Figure 3 · p. 7

3.2 SEQUENTIAL GRAPH REPRESENTATION OF SCALABLE ANALOG CIRCUIT TOPOLOGIES

  • Eulerian-circuit sequences store existing edges rather than sparse adjacency-matrix zeros and can represent any finite connected undirected topology after replacing each edge with two directed arcs.The directed graph contains an Eulerian circuit starting from any node.Source: §3.2 · pp. 5–6

3.3 DATA AUGMENTATION TO PREVENT OVER-FITTING AND REDUCE INDUCTIVE BIAS

  • Generating multiple Eulerian circuits per real-world topology yields 70× more data, while BFS node ordering and a VSS start address graph- and sequence-level permutation invariance.The method targets limitations of synthetic circuit data and the equivalent graph representations arising from node permutations.Source: §3.3 · p. 6

3.4 CUSTOMIZING TOKENIZER TO PRE-TRAIN A DOMAIN-SPECIFIC GPT MODEL

  • A customized pin-token tokenizer supports complete-topology pre-training from VSS, followed by fine-tuning for high-performance, task-specific unseen circuits.Device types and their maximum counts are determined from training data; a Truncate token and padding support variable device counts and fixed-length sequences.Source: §3.4 · pp. 6–7

4 RESULTS

AnalogGenie generates valid, scalable, and novel analog circuit topologies and achieves strong circuit-performance results. Data augmentation improves both validation loss and generation quality.

4.1 EXPERIMENT SETUP

  • The dataset contains 3350 topologies across 11 circuit types, with up to 54 devices; AnalogGenie is a 6-layer, 6-head decoder-only transformer with 11.825 million parameters.Training uses a 9:1 topology train-validation split followed by 70× sequence augmentation; validation topologies are therefore unseen.Source: §4.1 · p. 7
  • Evaluation generates Op-Amp, bandgap-reference, and power-converter topologies and assesses correctness, scalability, novelty, and best FoM after genetic-algorithm sizing.Correctness means simulatable with default sizing; novelty means differing from all dataset topologies.Source: §4.1 · pp. 7–8

4.2 ENHANCED GENERATION CAPABILITIES WITH DATA AUGMENTATION

  • Augmentation reduces validation loss by approximately 8.5× and increases valid-circuit generation by 73.5×, compared with training on 3015 rather than 227766 sequences.Without augmentation, AnalogGenie overfits and fails to generate valid circuits.Source: Figure 4 · p. 8, §4.2 · p. 8, Table 1 · p. 8

4.3 COMPARISONS WITH STATE-OF-THE-ARTS

  • AnalogGenie produces 73.5% valid circuits after pretraining and 93.2% after fine-tuning, versus 57.3% for AnalogCoder, 67.5% for CktGNN, and 68.2% for LaMAGIC.The paper attributes its correctness advantage to device pin-level representation, which explicitly defines connections and avoids mapping ambiguity.Source: §4.3 · pp. 8–9
  • AnalogGenie generates 11 circuit types zero-shot and circuits with up to 64 devices after pretraining and 56 after fine-tuning, compared with 7 types for AnalogCoder and maximum sizes of 4, 22, and 10 devices for LaMAGIC, CktGNN, and AnalogCoder.The dataset includes topologies with over 50 devices; the paper credits its sequential representation with capturing larger designs within a limited sequence length.Source: §4.3 · p. 9
  • AnalogGenie generates nearly 100% novel circuits, compared with 93.1% for CktGNN, 12.7% for LaMAGIC, and 8.9% for AnalogCoder.The paper links AnalogGenie’s novelty to its ability to design large circuits from scratch.Source: §4.3 · p. 9
  • For Op-Amps, AnalogGenie reaches FoM 19 after pretraining and 36.5 after fine-tuning, versus 10.9 for CktGNN and 1.7 for AnalogCoder.Fine-tuning focused on high-performance Op-Amp design.Source: §4.3 · p. 9
  • For power converters, AnalogGenie achieves FoM 2.5 versus LaMAGIC’s 2.2 and 3.3 after fine-tuning; it alone designs bandgap references, with FoM 17.2 pretrained and 21.9 fine-tuned.The paper attributes the fine-tuned power-converter gain to AnalogGenie’s larger design capacity.Source: §4.3 · p. 9

5 CONCLUSION AND FUTURE WORK

AnalogGenie combines a GPT-based circuit-topology generator with a comprehensive topology dataset and sequence-based graph representation, and experiments across three benchmark types demonstrate scalable discovery of unseen topologies. The authors identify improved sizing efficiency and potential extension to digital design as future directions.

Conclusion

  • Across three analog-circuit benchmark types, AnalogGenie efficiently discovers previously unseen topologies in a scalable manner.The engine uses a GPT model to predict the next device pin to connect within a circuit.Source: §5 · p. 9
  • The authors envision generative AI and IC design advancing each other, with IC design enhancing generative AI and generative AI accelerating IC design.Source: §5 · pp. 9–10

Limitations and future work

  • AnalogGenie combines topology generation with a genetic algorithm that optimizes generated circuits’ parameters, including sizing and bias.The work focuses on discovering topologies likely to achieve a superior FoM once sized.Source: §5 · p. 10
  • Future work could improve the sizing algorithm’s sample efficiency and combine AnalogGenie’s graph-generation approach with code generation for digital circuit development.The authors also suggest the expressive representation and bottom-up approach may generalize to digital design.Source: §5 · pp. 9–10

6 REPRODUCEBILITY STATEMENT

The paper supports reproducibility by identifying its theoretical proof and experimental setup, describing supplementary implementation resources, and reporting plans to release its code and dataset.

6 REPRODUCEBILITY STATEMENT

  • The proof of Theorem 3.2.1 appears in Section 3.2, while experiment setup and implementation details are described in Section 4.1.Source: §6 · p. 10
  • Supplementary material provides open-source code for data augmentation, pretraining, and finetuning, plus the genetic algorithm sizing framework and Ngpsice simulation infrastructure.Source: §6 · p. 10
  • Appendix A.1 reports statistics for the circuit dataset, and the authors say they will make the code and dataset public on Github in the future.Source: §6 · p. 10

A APPENDIX · A.1 DATASET STATISTICS

The appendix’s dataset-statistics subsection presents distributions of circuit device counts and topology types.

A.1 DATASET STATISTICS

  • Figure 5 presents the device-number distribution in the analog-circuit dataset.Source: Figure 5 · p. 13
  • Figure 6 presents the circuit topology type distribution in the analog-circuit dataset.Source: Figure 6 · p. 13

A.2 TOKENIZER LOOKUP TABLE

The tokenizer lookup table maps circuit elements to indices, covering both basic devices and multi-device logic gates. This broader vocabulary supports describing large digital circuits for mixed-signal designs.

A.2 TOKENIZER LOOKUP TABLE

  • The experiment’s tokenizer lookup table maps basic devices and multi-device logic gates to indices, extending its vocabulary to describe large digital circuits for mixed-signal designs.Source: §A.2 · p. 14, Table 2 · p. 14

A.3 MORE DETAILS ABOUT EULERIAN CIRCUIT AND DATA AUGMENTATION

The appendix illustrates an analog topology, its device pin-level graph representation, and four unique Eulerian circuits found using DFS.

A.3 MORE DETAILS ABOUT EULERIAN CIRCUIT AND DATA AUGMENTATION

  • The example pairs an analog topology with its device pin-level graph and shows four unique Eulerian circuits found using DFS.Source: Figure 7 · p. 15, §A.3 · p. 15

A.4 ANALOGGENIE’S GENERATED CIRCUIT TOPOLOGY VISUALIZATION … A.5 FAILED EXAMPLES GENERATED BY ANALOGGENIE PRE-TRAINED MODEL

The appendix presents manually drawn Cadence Virtuoso schematics of generated circuits, including novel examples, a zero-shot circuit type, and failed examples.

A.4 ANALOGGENIE’S GENERATED CIRCUIT TOPOLOGY VISUALIZATION

  • The appendix uses schematics manually drawn in Cadence Virtuoso, an industry-standard analog schematic editing tool, to visualize generated circuits.Source: §A.4 · p. 16

A.4.1 NOVEL CIRCUITS

  • AnalogGenie generated a novel op-amp with GBW = 12 MHz, CL = 100 pF, Power = 32.88 mW, and FoM = 36.5.Source: Figure 8 · p. 16
  • AnalogGenie generated a novel DC converter with Efficiency = 0.95, Voltage conversion ratio = 2.35, and FoM = 3.3.Source: Figure 9 · p. 16
  • AnalogGenie generated a novel bandgap reference with TC = 3 ppm/◦C, Line regulation = 0.196 %/V, PSRR = 70 dB, and FoM = 21.9.Source: Figure 10 · p. 17

A.4.2 ZERO-SHOT GENERATION

  • AnalogGenie generated a transconductance amplifier in a zero-shot example, although that circuit type was not included in the dataset.Source: §A.4 · p. 16, Figure 11 · p. 18

A.5 FAILED EXAMPLES GENERATED BY ANALOGGENIE PRE-TRAINED MODEL

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